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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2013)
Search Results: Keywords 'from:2013-11-27 to:2013-11-27'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 11:10 |
Kagoshima | A Quantizer Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)  CPM2013-113 ICD2013-90 |
To make full use of the advantages of dynamic voltage and frequency scaling (DVFS) technique, a quantization decoder (Q... [more] | CPM2013-113 ICD2013-90 pp.31-36 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 11:35 |
Kagoshima | Low Energy Tracking System with Dynamic Frame-Rate Optimization Serina Egawa, Koji Inoue (Kyushu Univ.) CPM2013-114 ICD2013-91 |
[more] | CPM2013-114 ICD2013-91 pp.37-42 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:00 |
Kagoshima | Exploring Microarchitecture for Next Generation Single-Flux-Quantum Processors Jumpei Yokota, Tomonori Tsuhata, Koji Inoue (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.) CPM2013-115 ICD2013-92 |
[more] | CPM2013-115 ICD2013-92 pp.43-48 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:25 |
Kagoshima | A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.) CPM2013-116 ICD2013-93 |
In this paper, a design methodology for realizing power efficient nonvolatile FPGA (NVFPGA) using magnetic tunnel juncti... [more] | CPM2013-116 ICD2013-93 pp.49-53 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:00 |
Kagoshima | [Invited Talk]
Circuit design for 3D-stacking using TSV interconnects Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi) VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41 |
To improve the performance of 3D-stacking using TSV interconnects, circuit techniques were developed. To improve Z-axis ... [more] | VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41 pp.93-96(VLD), pp.55-58(CPM), pp.55-58(ICD), pp.1-4(CPSY), pp.93-96(DC), pp.13-16(RECONF) |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:40 |
Kagoshima | [Invited Talk]
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.) VLD2013-74 CPM2013-118 ICD2013-95 CPSY2013-59 DC2013-40 RECONF2013-42 |
[more] | VLD2013-74 CPM2013-118 ICD2013-95 CPSY2013-59 DC2013-40 RECONF2013-42 pp.97-100(VLD), pp.59-62(CPM), pp.59-62(ICD), pp.5-8(CPSY), pp.97-100(DC), pp.17-20(RECONF) |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 15:30 |
Kagoshima | [Invited Talk]
Cu Wiring Technology for 3D/2.5D Packaging Motoaki Tani, Yoshihiro Nakata, Tsuyoshi Kanki, Tomoji Nakamura (Fujitsu Lab.) VLD2013-75 CPM2013-119 ICD2013-96 CPSY2013-60 DC2013-41 RECONF2013-43 |
[more] | VLD2013-75 CPM2013-119 ICD2013-96 CPSY2013-60 DC2013-41 RECONF2013-43 pp.101-106(VLD), pp.63-68(CPM), pp.63-68(ICD), pp.9-14(CPSY), pp.101-106(DC), pp.21-26(RECONF) |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 16:10 |
Kagoshima | [Invited Talk]
Chip Thinning Technologies for Chip Stacking Packages Shinya Takyu, Tetsuya Kurosawa (Toshiba) VLD2013-76 CPM2013-120 ICD2013-97 CPSY2013-61 DC2013-42 RECONF2013-44 |
[more] | VLD2013-76 CPM2013-120 ICD2013-97 CPSY2013-61 DC2013-42 RECONF2013-44 pp.107-112(VLD), pp.69-74(CPM), pp.69-74(ICD), pp.15-20(CPSY), pp.107-112(DC), pp.27-32(RECONF) |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 08:55 |
Kagoshima | System-level design method considering the interrupt processing Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.) VLD2013-77 DC2013-43 |
We propose a system level design methodology for control systems that have both input and output by abstraction of inter... [more] | VLD2013-77 DC2013-43 pp.119-124 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:20 |
Kagoshima | Function-Level Profiling for Embedded Software with QEMU Tran Van Dung, Ittetsu Taniguchi (Ritsumeikan Univ.), Takuji Hieda (Kyushu Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-78 DC2013-44 |
Function-level profiling is crucial for optimized embedded software which needs to have resource constraint, low level p... [more] | VLD2013-78 DC2013-44 pp.125-128 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:25 |
Kagoshima | Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo) VLD2013-80 DC2013-46 |
[more] | VLD2013-80 DC2013-46 pp.135-140 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:50 |
Kagoshima | Energy evaluation of writing reduction method for non-volatile memory Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-81 DC2013-47 |
Non-volatile memory has many advantages over SRAM, such as high density, low leakage power, and non-volatility. However... [more] |
VLD2013-81 DC2013-47 pp.141-146 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 11:15 |
Kagoshima | Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers Yudai Itoi, Shinji Kimura (Waseda Univ.) VLD2013-82 DC2013-48 |
Recently, the next generation non-volatile memory/register using magnetic tunnel junction elements has been paid attenti... [more] | VLD2013-82 DC2013-48 pp.147-152 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 13:20 |
Kagoshima | Evaluations of Variations on Ring Oscillators from Plasma Induced Damage in Bulk and SOTB Processes Ryo Kishida, Michitarou Yabuuchi, Azusa Oshima, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2013-83 DC2013-49 |
A degradation of reliability caused by plasma induced damage has become a significant concern with miniaturizing a devic... [more] | VLD2013-83 DC2013-49 pp.159-164 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 13:45 |
Kagoshima | A Study on Design Structure of Ring Oscillators with Plural Frequency Characteristics in FPGAs Yousuke Miyake, Masafumi Monden, Yasuo Sato, Seiji Kajihara (Kyusyu Inst. of Tech.) VLD2013-84 DC2013-50 |
FPGAs are used in various embedded systems including highly reliable systems, therefore, it is important to ensure its r... [more] | VLD2013-84 DC2013-50 pp.165-170 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 14:10 |
Kagoshima | An inverter block construction method to reduce test data volume on BAST Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ), Michinobu Nakao (Yomiuri Institute) VLD2013-85 DC2013-51 |
BAST is one of technique to reduce the amount of test data while maintaining the high test quality using built-in self t... [more] | VLD2013-85 DC2013-51 pp.171-176 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 17:00 |
Kagoshima | [Keynote Address]
The age of Space Discovery Opened by World's First Solar Sail "IKAROS" Osamu Mori (JAXA) VLD2013-86 CPM2013-121 ICD2013-98 CPSY2013-62 DC2013-52 RECONF2013-45 |
A solar power sail is a Japanese original concept that gets electricity from thin film solar cells on the solar sail in ... [more] | VLD2013-86 CPM2013-121 ICD2013-98 CPSY2013-62 DC2013-52 RECONF2013-45 pp.177-181(VLD), pp.75-79(CPM), pp.75-79(ICD), pp.21-25(CPSY), pp.177-181(DC), pp.33-37(RECONF) |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 08:30 |
Kagoshima | Soft-core microprocessor for small reconfigurable device Yuichi Watanabe, Taisuke Yamamoto, Yuki Yoshida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2013-46 |
This paper proposes a soft-core processor implemented by using hardware description language that is possible to be imp... [more] |
RECONF2013-46 pp.39-44 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 08:55 |
Kagoshima | Mapping of Java bytecode to virtual CGRA with implementation in FPGA Yuki Ogawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-47 |
In embedded systems, the needs for rapid both low-cost development and high performance has been increasing recently. ... [more] |
RECONF2013-47 pp.45-50 |
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