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Technical Committee on Hardware Security (HWS) (Searched in: 2018)
Search Results: Keywords 'from:2019-02-27 to:2019-02-27'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2019-02-27 10:25 |
Okinawa | Okinawa Ken Seinen Kaikan | FPGA Implementation of Fully Convolutional Network for Semantic Segmentation Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech)  VLD2018-93 HWS2018-56 |
[more] | VLD2018-93 HWS2018-56 pp.1-6 |
| HWS, VLD | 2019-02-27 10:50 |
Okinawa | Okinawa Ken Seinen Kaikan | Spatial-Separable Convolution: Low memory CNN for FPGA Akira Jinguji, Masayuki Shimoda, Hiroki Nakahara (titech) VLD2018-94 HWS2018-57 |
Object detection and image recognition using a Convolutional Neural Network (CNN) are used in embedded systems, which re... [more] | VLD2018-94 HWS2018-57 pp.7-12 |
| HWS, VLD | 2019-02-27 11:15 |
Okinawa | Okinawa Ken Seinen Kaikan | A Case Study on Approximate Multipliers for MNIST CNN Kenta Shirane, Takahiro Yamamoto (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-95 HWS2018-58 |
[more] | VLD2018-95 HWS2018-58 pp.13-18 |
| HWS, VLD | 2019-02-27 12:40 |
Okinawa | Okinawa Ken Seinen Kaikan | Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2018-96 HWS2018-59 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2018-96 HWS2018-59 pp.19-24 |
| HWS, VLD | 2019-02-27 13:05 |
Okinawa | Okinawa Ken Seinen Kaikan | Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60 |
In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] | VLD2018-97 HWS2018-60 pp.25-30 |
| HWS, VLD | 2019-02-27 13:30 |
Okinawa | Okinawa Ken Seinen Kaikan | Routing Algorithm to Achieve Circular Wire for SIM-Type SADP Shun Akatsuka, Kunihiro Fujiyoshi (TUAT) VLD2018-98 HWS2018-61 |
Wires of Spacer-Is-Metal (SIM) type Self-Aligned Double Patterning (SADP) is peculiar since wires is circular when dummy... [more] | VLD2018-98 HWS2018-61 pp.31-36 |
| HWS, VLD | 2019-02-27 13:55 |
Okinawa | Okinawa Ken Seinen Kaikan | Set-Pair Routing Algorithm with Selective Pin-Pair Connections Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2018-99 HWS2018-62 |
We propose a set-pair routing algorithm which efficiently generates a length matched routing pattern. In our algorithm, ... [more] | VLD2018-99 HWS2018-62 pp.37-42 |
| HWS, VLD | 2019-02-27 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan | Function-level Module Sharing with High-level Synthesis Ryohei Nozaki (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-100 HWS2018-63 |
High-Level Synthesis (HLS) which automatically synthesizes a Resister-Transfer Level (RTL) circuit from a behavioral des... [more] | VLD2018-100 HWS2018-63 pp.43-48 |
| HWS, VLD | 2019-02-27 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan | High-Level Synthesis of the CHStone Benchmark Programs with SDSoC Takuya Adachi (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-101 HWS2018-64 |
In recent years, High-Level Synthesis (HLS), which automatically generates hardware circuits from software program, have... [more] | VLD2018-101 HWS2018-64 pp.49-54 |
| HWS, VLD | 2019-02-27 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan | Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework Masataka Aoki, Yukihide Kohira (Univ. of Aizu) VLD2018-102 HWS2018-65 |
In general-synchronous framework (g-frame), in which a clock is not assumed to be distributed to all registers simultane... [more] | VLD2018-102 HWS2018-65 pp.55-60 |
| HWS, VLD | 2019-02-27 15:45 |
Okinawa | Okinawa Ken Seinen Kaikan | Timing Correction by Constrained Temperature Dependent Clock Skew Mineo Kaneko (JAIST) VLD2018-103 HWS2018-66 |
This report treats temperature dependent clock skew scheduling for a general class of sequential circuits. Previous stud... [more] | VLD2018-103 HWS2018-66 pp.61-66 |
| HWS, VLD | 2019-02-27 16:20 |
Okinawa | Okinawa Ken Seinen Kaikan | A Battery Degradation aware System Level Battery Management Methodology Daichi Watari, Ittetsu Taniguchi, Takao Onoye (Osaka Univ.) VLD2018-104 HWS2018-67 |
The battery degradation is a serious problem for the modern electrical systems. This paper proposes State of Health (SOH... [more] | VLD2018-104 HWS2018-67 pp.67-72 |
| HWS, VLD | 2019-02-27 16:45 |
Okinawa | Okinawa Ken Seinen Kaikan | Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-105 HWS2018-68 |
FPGA-based manycore architectures attract an increasing attention in order to realize high-performance embedded systems.... [more] | VLD2018-105 HWS2018-68 pp.73-78 |
| HWS, VLD | 2019-02-27 17:10 |
Okinawa | Okinawa Ken Seinen Kaikan | Improvement on DMA Transfer Efficiency by Packet Concatenation Shoko Ohteru, Saki Hatta, Tomoaki Kawamura, Koji Yamazaki, Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) VLD2018-106 HWS2018-69 |
(To be available after the conference date) [more] | VLD2018-106 HWS2018-69 pp.79-84 |
| HWS, VLD | 2019-02-28 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Thermal transient analysis and evaluation of the heat generation and dissipation in three-dimensional stacked LSI Ryota Horigome, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2018-107 HWS2018-70 |
As a technology for improving the degree of integration of LSI, there is a three-dimensional stacking technology of LSI ... [more] | VLD2018-107 HWS2018-70 pp.85-90 |
| HWS, VLD | 2019-02-28 10:25 |
Okinawa | Okinawa Ken Seinen Kaikan | Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB Ryo Magasaki, Yusuke Yoshida (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2018-108 HWS2018-71 |
In recent years, IoT devices are rapidly increasing. One of the IoT devices is a sensor node and a small medical device... [more] | VLD2018-108 HWS2018-71 pp.91-96 |
| HWS, VLD | 2019-02-28 10:50 |
Okinawa | Okinawa Ken Seinen Kaikan | Single Supply Level Shifter Circuit using body-bias Yuki Takeyoshi, Kimiyoshi Usame (SIT) VLD2018-109 HWS2018-72 |
A multi-VDD scheme exists as a technique to realize low power consumption by using different power supply voltages. A ci... [more] | VLD2018-109 HWS2018-72 pp.97-102 |
| HWS, VLD | 2019-02-28 11:15 |
Okinawa | Okinawa Ken Seinen Kaikan | Implementation Technology for the Advanced Wafer Manufacturing Processes on Optical Transmission LSIs Susumu Hirano, Hideo Yoshida, Kenya Sugihara, Yoshiaki Konishi, Takashi Sugihara, Yoshihiro Ogawa (Mitsubishi Electric) VLD2018-110 HWS2018-73 |
It is indispensable to use the advanced wafer manufacturing processes to develop LSIs of high-speed optical transmission... [more] | VLD2018-110 HWS2018-73 pp.103-108 |
| HWS, VLD | 2019-02-28 12:40 |
Okinawa | Okinawa Ken Seinen Kaikan | * Yuka Aizawa, Masashi Tawada (Waseda Univ.), Yuta Ideguchi, Norifumi Kamiya (NEC), Nozomu Togawa (Waseda Univ.) VLD2018-111 HWS2018-74 |
(To be available after the conference date) [more] | VLD2018-111 HWS2018-74 pp.109-114 |
| HWS, VLD | 2019-02-28 13:05 |
Okinawa | Okinawa Ken Seinen Kaikan | High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology Kazuki Niino, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-112 HWS2018-75 |
Domino logic was introduced at the forefront of the LSI market in the 2000s for high-speed circuits. In recent years, h... [more] | VLD2018-112 HWS2018-75 pp.115-120 |
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