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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2024-01-31 12:35 |
Tokyo | KIT Toranomon Graduate School (Primary: On-site, Secondary: Online) |
[Invited Talk]
Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs Hiroshi Oka, Hidehiro Asai, Takumi Inaba, Shunsuke Shitakata, Hitoshi Yui, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Takashi Nakayama, Takahiro Mori (AIST)  SDM2023-74 |
Toward large-scale quantum computers, cryogenic CMOS circuits have been developed to control and readout the qubits insi... [more] | SDM2023-74 pp.1-4 |
| NLP, CAS | 2023-10-06 14:50 |
Gifu | Work plaza Gifu | A Design and Evaluation of the Up/Down Counter Type PWM Adder Using the Subthreshold Region Gaku Abe, Andrino Robles Roberto, Takumi Nihei, Tomochika Harada (Yamagata Univ.) CAS2023-42 NLP2023-41 |
This paper presents the design and evaluation of a PWM adder circuit using up/down counters operating in the subthreshol... [more] | CAS2023-42 NLP2023-41 pp.53-57 |
| NLP, CAS | 2023-10-06 15:10 |
Gifu | Work plaza Gifu | A PWM/digital Converter for Improved Conversion Resolution using Frequency Multiplicator Zhang He, Andrino Robles Roberto, Tomochika Harada (Yamagata Univ.) CAS2023-43 NLP2023-42 |
For IoT (Internet of Things) devices, a reduction in power consumption is desired. To reduce power consumption, researc... [more] | CAS2023-43 NLP2023-42 pp.58-61 |
| CCS | 2023-03-26 10:55 |
Hokkaido | RUSUTSU RESORT | A Stochastic Memory for Ultralow-Power IoT Devices and its Subthreshold CMOS Circuit Implementation Seiya Muramatsu, Kohei Nishida, Kota Ando (Hokkaido Univ.), Megumi Akai-Kasaya (Osaka Univ./Hokkaido Univ.), Tetsuya Asai (Hokkaido Univ.) CCS2022-68 |
We propose a CMOS circuit implementation of a memory circuit for ultralow-power IoT devices based on stochastic computin... [more] | CCS2022-68 pp.31-35 |
| EE | 2023-01-20 11:25 |
Fukuoka | Kyushu Institute of Technology (Primary: On-site, Secondary: Online) |
Online junction temperature measurement of Power MOSFET by dynamic VGS-ID monitoring system Yandagkhuu Bayarsaikhan, Ichiro Omura (KIT) EE2022-46 |
As the demand for high reliability in power electronics systems increases, the online condition monitoring of power devi... [more] | EE2022-46 pp.111-116 |
| ICD, SDM, ITE-IST [detail] | 2022-08-08 14:15 |
Online | Evaluation of Steep Subthreshold Slope Device "Dual-gate type PN-body Tied SOI-FET" for Ultra-low Voltage Operation Haruki Yonezaki, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC) SDM2022-38 ICD2022-6 |
In this study, we report the first prototype results of a Steep SS "Dual-Gate (DG) PN-Body Tied (PNBT) SOI-FET" for extr... [more] | SDM2022-38 ICD2022-6 pp.17-20 |
|
| ED | 2022-04-21 11:00 |
Online | Online | TIQ Based Flash ADC with Threshold Compensation Yuhei Hashimoto, Cong-Kha Pham (UEC) ED2022-5 |
It is known that Analog-to-digital converter using TIQ comparators are vulnerable to process and temperature variations,... [more] | ED2022-5 pp.15-18 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 09:40 |
Ehime | Ehime Prefecture Gender Equality Center | Device characteristic measurement for realizing CMOS-compatible non-volatile memory using FiCC Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2019-36 DC2019-60 |
This report proposes a new non-volatile memory element that can be fabricated with a standard CMOS process, and that can... [more] | VLD2019-36 DC2019-60 pp.63-68 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 09:00 |
Hiroshima | Satellite Campus Hiroshima | Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-65 DC2018-51 |
This report proposes a new non-volatile memory element that can be fabricated with a standard CMOS process, and that can... [more] | VLD2018-65 DC2018-51 pp.183-188 |
| SDM | 2018-10-18 14:00 |
Miyagi | Niche, Tohoku Univ. | Statistical Analysis of Electric Characteristics Variability Using MOSFETs with Asymmetric Source and Drain Shinya Ichino, Akinobu Teramoto, Rihito Kuroda, Takezo Mawaki, Tomoyuki Suwa, Shigetoshi Sugawa (Tohoku Univ.) SDM2018-62 |
In this paper, a statistical analysis of electric characteristics variabilities such as threshold voltage variability an... [more] | SDM2018-62 pp.51-56 |
| SRW | 2018-08-20 15:25 |
Okayama | Okayama Univ. | [Invited Talk]
Indoor Localization Using IR-UWB and Effective Approaches for Performance Improvement Li Huan-Bang, Ryu Miura, Toshinori Kagawa, Fumihide Kojima (NICT) SRW2018-19 |
The authors have been developing and evaluating IR-UWB positioning system. A mobile node performs time-of-arrival (TOA) ... [more] | SRW2018-19 pp.57-62 |
| SDM, ICD, ITE-IST [detail] | 2018-08-07 15:00 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | A 0.6V 9bit PWM Differential Arithmetic Circuit Fumiya Kojima, Tomochika Harada (Yamagata Univ) SDM2018-32 ICD2018-19 |
In this paper, we design and evaluate the analog / PWM conversion circuit and the PWM differential arithmetic circuit wh... [more] | SDM2018-32 ICD2018-19 pp.35-40 |
| VLD, HWS (Joint) |
2018-02-28 17:45 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104 |
Moore's Law has been miniaturizing integrated circuits, which can make a lot of high performance devices such as PCs an... [more] |
VLD2017-104 pp.91-96 |
| VLD, HWS (Joint) |
2018-03-02 09:00 |
Okinawa | Okinawa Seinen Kaikan | On-chip and ultra low current measurement circuit based on potentiostat method Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2017-119 |
We propose a current measurement circuit using on - chip high resistance by MOSFET. Due to advances in biosensing techno... [more] | VLD2017-119 pp.181-186 |
| SDM, ICD, ITE-IST [detail] | 2017-08-01 13:50 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | Evaluation of equivalent MOSFET reduced temperature dependence of threshold voltage Takuya Yamaguchi, Tatsuya Oku, Kawori Sekine (Meiji Univ.) SDM2017-41 ICD2017-29 |
A MOSFET has a temperature dependence of threshold voltage and mobility. In this paper, we focused on threshold voltage ... [more] | SDM2017-41 ICD2017-29 pp.77-82 |
| VLD | 2017-03-02 09:25 |
Okinawa | Okinawa Seinen Kaikan | FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration Naoyuki Miyagawa, Tomoya Kimura, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2016-109 |
In this paper, we propose Fishbone-in-Cage Capacitor (FiCC) that is a new variant of metal fringe capacitor (MFC), and s... [more] | VLD2016-109 pp.43-47 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 12:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | 2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting Tomoya Kimura, Hiroyuki ochi (Ritsumeikan Univ.) VLD2016-46 DC2016-40 |
This report proposes L1L5-type 2-step charge pump circuit that is suitable for boosting efficiently the subthreshold inp... [more] | VLD2016-46 DC2016-40 pp.13-18 |
| ICD, SDM, ITE-IST [detail] | 2016-08-02 09:00 |
Osaka | Central Electric Club | [Invited Talk]
Soft Error Immunity of Ultra-Low Voltage SRAM Masanori Hashimoto (Osaka Univ.) SDM2016-54 ICD2016-22 |
This paper discusses soft error immunity of near-threshold/subthreshold SRAM. In terrestrial environment, high-energy ne... [more] | SDM2016-54 ICD2016-22 pp.53-58 |
| VLD | 2016-03-01 17:30 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2015-131 |
A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchrono... [more] | VLD2015-131 p.117 |
| ICD, ITE-IST | 2015-07-03 14:20 |
Kanagawa | National Defense Academy | [Invited Talk]
Circuit Design Techniques for Low Power Energy Harvesting System
-- Efficient DC-DC Boost Converter and Ultra-Low Power Digital Circuits -- Mitsuji Okada, Yuzuru Shizuku, Tetsuya Hirose (Kobe Univ.) ICD2015-22 |
In this paper, we present the circuit design techniques for an efficient DC-DC boost converter, a MPPT (Maximum Power Po... [more] | ICD2015-22 pp.47-52 |
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