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 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
OCS, CS
(Joint)		 2023-01-13
10:15		 Fukuoka CANAL CITY HAKATA
(Primary: On-site, Secondary: Online)		 Inter-core skew and mode-dependent loss degrade Q2 in long-haul coupled-core multicore fibre transmission
Shohei Beppu, Daiki Soma, Noboru Yoshikane, Takehiro Tsuritani (KDDI Research) OCS2022-65		 To dramatically increase the transmission capacity of optical backbone network systems, space division multiplexing (SDM... [more] OCS2022-65
pp.27-32
ICD, CPSY, CAS 2017-12-14
15:10		 Okinawa Art Hotel Ishigakijima Proposal of high precision skew adjustment method with an on-chip setup time measurement circuit
Naoto Kamba, Masaki Ishii, Masahiro Sasaki (SIT) CAS2017-84 ICD2017-72 CPSY2017-81		 In recent years, clock skew which can be tolerated is reduced because the operating speed of integrated circuits increas... [more] CAS2017-84 ICD2017-72 CPSY2017-81
p.97
VLD 2017-03-02
15:50		 Okinawa Okinawa Seinen Kaikan MILP Approach to Skew-Aware High Level Synthesis
Kai Shimura, Mineo Kaneko (JAIST) VLD2016-120		 Intentional clock skew is known as one of the promising techniques for enhancing the circuit speed.
However, when we tr... [more]		 VLD2016-120
pp.97-102
VLD, CAS, MSS, SIP 2016-06-17
15:10		 Aomori Hirosaki Shiritsu Kanko-kan Clock Distribution Network with Multiple Source Buffers for Stacked Chips
Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31		 In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31
pp.167-172
VLD 2010-03-12
10:50		 Okinawa   High-Level Design Conditions for Post-Fabrication Timing-Adjustable Datapaths
Akira Tehara, Mineo Kaneko (JAIST) VLD2009-122		 With the progress of fabrication-process technology, the variation of signal transmission delay due to
variations in pr... [more]		 VLD2009-122
pp.139-144
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
16:35		 Kanagawa   A Tunable LSI Based on Timing Skew and Stall Adjustments
Yayumi Uehara, Mineo Kaneko (JAIST) VLD2008-106 CPSY2008-68 RECONF2008-70		 With the advance of process technologies, delay variations become relatively larger. As a result, it becomes difficult t... [more] VLD2008-106 CPSY2008-68 RECONF2008-70
pp.87-92
ICD, ITE-IST 2007-07-27
08:55		 Hyogo   A 1GHz to 2GHz 4-Phase On-Chip Clock Generator with Timing Margin Test Capability
Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno (NEC) ICD2007-55		 A functional clock generator presented here makes timing margin testing possible. The clock generator provides the follo... [more] ICD2007-55
pp.107-112
 Results 1 - 7 of 7  /   
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