Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
US |
2011-04-28 13:25 |
Tokyo |
The University of Electro-Communications |
Estimation of sound field formed by parametric array using numerical simulation
-- Application to self-silenced sound beam -- Hideyuki Nomura (UEC), Claes M. Hedberg (BTH), Tomoo Kamakura (UEC) US2011-2 |
This study proposes a numerical calculation method that simulates a nonlinear propagation of ultrasound beams, estimatin... [more] |
US2011-2 pp.7-12 |
DC, CPSY |
2011-04-12 13:25 |
Tokyo |
|
A Note on Data Compression of Double-Precision Floating-Point Numbers for Massively Parallel Numerical Simulations Mamoru Ohara, Takashi Yamaguchi (TIRI) CPSY2011-2 DC2011-2 |
In numerical simulations using massively parallel computers like GPGPU (General-Purpose computing on Graphics Processing... [more] |
CPSY2011-2 DC2011-2 pp.5-10 |
DC |
2010-02-15 15:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
High Speed X-Fault Diagnosis with Partial X-Resolution Kohei Miyase (Kyushu Inst. of Tech.), Yusuke Nakamura (Panasonic Communications Software Co.,Ltd.), Yuta Yamato, Xiaoqing Wen, Seiji Kajihara (Kyushu Inst. of Tech.) DC2009-76 |
Defects behavior of ultra small size and high speed LSI is getting complicated. It makes localization of fault site and ... [more] |
DC2009-76 pp.69-74 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 15:40 |
Kochi |
Kochi City Culture-Plaza |
Two-level Cache Simulation with L2 Unified Cache for Embedded Applications Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-47 DC2009-34 |
In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simula... [more] |
VLD2009-47 DC2009-34 pp.37-42 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 16:00 |
Kochi |
Kochi City Culture-Plaza |
Simulation-Based Bus Width Optimization for Two-Level Cache Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-48 DC2009-35 |
In this paper, we propose a simulation-based bus width and cache configuration optimization approach for two-level cache... [more] |
VLD2009-48 DC2009-35 pp.43-48 |
TL |
2009-07-19 10:35 |
Fukuoka |
New Century Plaza II, Hakozaki Campus of Kyushu Univ. |
Does implicit grammatical person influence perspective in mental simulation? Manami Sato, Benjamin K. Bergen (Univ. of Hawaii) TL2009-21 |
Language comprehension causes the retrieval of listeners prior perceptual and motor experiences, and this retrieval gene... [more] |
TL2009-21 pp.73-77 |
IN, NS (Joint) |
2009-03-04 08:20 |
Okinawa |
Okinawa-Zanpamisaki Royal Hotel |
Analysis of maximum-bandwidth ALM tree on tree network Takamichi Kikkawa, Takamichi Miyata, Katsunori Yamaoka (Tokyo Inst. of Tech.) IN2008-174 |
It is important to use an ALM (application layer multicast) tree with broad bandwidth for quality of streaming applicati... [more] |
IN2008-174 pp.249-254 |
CAS, NLP |
2009-01-22 15:30 |
Miyazaki |
|
An Implementation in to the Circuit Simulation of Implicit Runge-Kutta Methods Yutaka Takakura, Yasuhiko Tohyama, Jun Shirataki, Makiko Okumura (KAIT) CAS2008-77 NLP2008-107 |
This paper describes an implementation method of implicit Runge-Kutta algorithm to the circuit simulation.We propose the... [more] |
CAS2008-77 NLP2008-107 pp.75-80 |
CAS, NLP |
2009-01-22 15:50 |
Miyazaki |
|
A Variable Time Step Method of Implicit Runge-Kutta Algorithm for Circuit Simulation Yasuhiko Tohyama, Yutaka Takakura, Jun Shirataki, Makiko Okumura (KAIT) CAS2008-78 NLP2008-108 |
This paper describs the algorithm of the variable time step when implicit Runge-Kutta(IRK) methods were applied to the c... [more] |
CAS2008-78 NLP2008-108 pp.81-86 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:30 |
Fukuoka |
Kitakyushu Science and Research Park |
A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-76 DC2008-44 |
In an embedded system where a single application or a class of applications are repeatedly executed on a processor, its ... [more] |
VLD2008-76 DC2008-44 pp.97-102 |