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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:40 |
Fukuoka | Kitakyushu Science and Research Park | Coarse-Grained Reconfigurable Architecture with Flexible Reliability Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.)  VLD2008-73 DC2008-41 |
Acceptable soft error rate on a VLSI chip varies depending on applications and operating environment so that recent VLSI... [more] | VLD2008-73 DC2008-41 pp.79-84 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:00 |
Fukuoka | Kitakyushu Science and Research Park | A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-42 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-42 pp.21-26 |
| RECONF | 2008-09-26 10:30 |
Okayama | Okayama Univ. | Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-33 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | RECONF2008-33 pp.63-68 |
| RECONF | 2008-09-26 11:00 |
Okayama | Okayama Univ. | Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2008-34 |
Dynamically Reconfigurable Processing Array (DRPA) have been received an attention as a flexible and efficient off-loadi... [more] | RECONF2008-34 pp.69-74 |
| SR | 2008-08-01 10:00 |
Tokyo | NICT (Koganei,-city Tokyo) | [Technology Exhibit]
Study on a Reconfigurable RF Frontend
-- A Band-Tunable Isolator -- Takayuki Furuta, Atsushi Fukuda, Hiroshi Okazaki, Shoichi Narahashi (NTTDoCoMo) SR2008-36 |
A reconfigurable RF front-end is a promising candidate for future multi-band mobile terminals. A band-tunable isolator ... [more] | SR2008-36 pp.119-122 |
| RECONF | 2008-05-22 16:05 |
Fukushima | The University of Aizu | A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-8 pp.43-48 |
| RECONF | 2008-05-23 09:00 |
Fukushima | The University of Aizu | Designing And Evaluating Dynamically Reconfigurable Processor with Power Gating Technique Yoshiki Saito (Keio Univ.), Toshiaki Shirai (Shibaura Inst.), Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami (Shibaura Inst.), Hideharu Amano (Keio Univ.) RECONF2008-10 |
A dynamically reconfigurable processor achieves high performance making the best use of high degree of parallelism with ... [more] | RECONF2008-10 pp.55-60 |
| SIS | 2008-03-13 11:15 |
Tokyo | Musashi Institute of Technology(Setagaya) | An Architecture of Dynamically Reconfigurable Systolic Array Toshiyuki Ishimura, Akinori Kanasugi (TDU) SIS2007-70 |
The Dynamically Reconfigurable Device which has high-speed performance of ASIC, flexibility of FPGA and high area effici... [more] | SIS2007-70 pp.11-16 |
| VLD, ICD | 2008-03-07 15:45 |
Okinawa | TiRuRu | A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University) VLD2007-167 ICD2007-190 |
Reed-Solomon Decoder can correct continues error and it has been a popular technology for various devices such as commu... [more] |
VLD2007-167 ICD2007-190 pp.65-68 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 11:05 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-123 CPSY2007-66 RECONF2007-69 |
This paper describes the physical design and evaluation of 3-D dynamically reconfigurable processor MuCCRA-Cube which co... [more] | VLD2007-123 CPSY2007-66 RECONF2007-69 pp.31-36 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-33 |
Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained types, its structure can ... [more] |
RECONF2007-33 pp.7-12 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 16:10 |
Fukuoka | Kitakyushu International Conference Center | Power analysis on Dynamic Reconfigurable Processor Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) RECONF2007-41 |
Dynamically Reconfigurable Processors have been expected to improve area and power eciency with the time-multiplexed ex... [more] | RECONF2007-41 pp.31-36 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 09:50 |
Fukuoka | Kitakyushu International Conference Center | An Implementation of Operating System Functions for a Reconfigurable System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2007-45 |
Reconfigurable devices have flexible hardware structures and realize high performance with parallelism. Reconfigurable s... [more] | RECONF2007-45 pp.13-18 |
| RECONF | 2007-09-21 10:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | An Implementation of Operating System Functions for a Reconfigurable System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) |
Reconfigurable devices have flexible hardware structures and realize high performance with parallelism. Reconfigurable s... [more] | |
| RECONF | 2007-05-17 13:00 |
Ishikawa | Kanazawa Bunka Hall | Query-Transaction Accelaration Appliance with a DRP using Stateful Packet-by-Packet Self-Reconfiguration Takashi Isobe (Hitachi) RECONF2007-1 |
Ubiquitous computing and the upcoming broadcast-and-communication convergence are making the need for high speed process... [more] | RECONF2007-1 pp.1-6 |
| RECONF | 2007-05-17 15:10 |
Ishikawa | Kanazawa Bunka Hall | 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication MuCCRA-Cube Shotaro Saito, Yohei Hasegawa, Yoshinori Kohama, Yasufumi Sugimori, Hideharu Amano (Keio Univ.) RECONF2007-5 |
In typical dynamically reconfiguarable devices, the overhead for programmable wires often forms critical paths by stretc... [more] | RECONF2007-5 pp.25-30 |
| RECONF | 2007-05-17 16:10 |
Ishikawa | Kanazawa Bunka Hall | Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits Yoshiaki Satou, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-7 |
Reconfigurable logic devices are classified into two type of logic block, which are coarse-grain and fine-grain by the b... [more] | RECONF2007-7 pp.37-42 |
| RECONF | 2007-05-18 09:30 |
Ishikawa | Kanazawa Bunka Hall | Power Reduction of Dynamical Reconfigurable Processor MuCCRA Keiichiro Hirai (Keio Univ.), Seidai Takeda (SIT.), Takashi Nishimura, Youhei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Kimiyoshi Usami (SIT.), Hideharu Amano (Keio Univ.) RECONF2007-11 |
Although dynamically recon gurable processors have received an attention as a cost-e ective o -load engine for mobile d... [more] |
RECONF2007-11 pp.61-66 |
| RCS, MoNA, WBS, SR, MW (Joint) |
2007-03-09 09:20 |
Kanagawa | YRP | Adaptive Reduction of Power Consumption of Viterbi Decoder using Reconfigurable Processor Yuken Kishimoto, Shinichiro Haruyama, Masao Nakagawa (Keio Univ.) SR2006-90 |
In past time, the research that Viterbi decoder is achieved on VLSI was studied, but it was unique research that Viterbi... [more] | SR2006-90 pp.9-13 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-18 13:00 |
Tokyo | Keio Univ. Hiyoshi Campus | Construction Method for a Circuit by Multiplication Satoshi Yano, Hayato Higuchi, Taichi Nagamoto, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
It shows that a connected graph which is composed of nodes which with max three links can be constructed to apply three ... [more] | VLD2006-99 CPSY2006-70 RECONF2006-70 pp.31-35 |
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