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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2013-04-12 08:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
Complementary atom-switch based programmable cell array and its demostraion of logic mapping synthesized from RTL code Makoto Miyamura, Munehiro Tada, Toshitsugu Sakamoto, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada (LEAP)  ICD2013-12 |
Reconfigurable nonvolatile programmable-logic using complementary atom switch (CAS) is successfully demonstrated on a 65... [more] | ICD2013-12 pp.55-59 |
| RECONF | 2012-05-29 11:25 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Optimization of PE Array Interconnection on CMA to Reduce Configuration Data Rie Uno (keio Univ.), Nobuaki Ozaki, Hideharu Amano (Keio Univ.) RECONF2012-6 |
Cool Mega Array or CMA is a low power reconfigurable processor array for battery driven mobile devices.We developed a ... [more] |
RECONF2012-6 pp.31-36 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-25 16:20 |
Kanagawa | Hiyoshi Campus, Keio University | A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP Akiko Hirao, Hidetoshi Takeshita, Haruka Yonezu, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) VLD2011-102 CPSY2011-65 RECONF2011-61 |
Recently, the Internet is necessary tool for our daily lives, and the number of the Internet users is increasing particu... [more] | VLD2011-102 CPSY2011-65 RECONF2011-61 pp.67-72 |
| SAT | 2011-12-13 13:55 |
Aichi | Nagoya University | Acquisition and tracking in inter-satellite communication with dynamically reconfigurable optical device Kaori Nishimaki, Atsushi Okamoto, Yuta Wakayama, Akihisa Tomita (Hokkaido Univ.), Yoshihisa Takayama (NICT) SAT2011-62 |
We propose an innovative acquisition and tracking system using a dynamically reconfigurable optical device for optical i... [more] | SAT2011-62 pp.137-140 |
| RCS, SAT (Joint) |
2011-08-26 10:20 |
Niigata | Niigata Univ. | Evaluation of a 16APSK RF signal Direct-Processing Transmitter and Receiver in high-efficiency modulation for Reconfigurable Communication Equipment in a small experiment satellite Midori Kato, Shiro Yoshikawa, Tamio Okui, Tetsuya Watanabe (NEC), Masayoshi Yoneda (NTSpace), Kenji Suzuki, Ryutaro Suzuki (NICT) SAT2011-31 |
This paper describes an evaluation of a 16APSK RF signal Direct-Processing Transmitter and Receiver designed for the Rec... [more] | SAT2011-31 pp.81-86 |
| RECONF | 2011-05-13 11:10 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation and Evaluation of a low power accelerator SLD-2 Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2011-16 |
Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobil... [more] | RECONF2011-16 pp.91-96 |
| CS, SIP, CAS | 2011-03-03 10:50 |
Okinawa | Ohhamanobumoto memorial hall (Ishigaki)( | A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (Tokyo Univ. of Agric and Tech.) CAS2010-128 SIP2010-144 CS2010-98 |
As multi-processor based computers and electronic devices become the norm, a further emphasis is made on achieving task... [more] |
CAS2010-128 SIP2010-144 CS2010-98 pp.155-160 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:00 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems Tomonori Izumi (Ritsumeikan Univ.) VLD2010-101 CPSY2010-56 RECONF2010-70 |
Reconfigurable logic devices are expected to be key devices to implement real-time, low-power, small autonomous recognit... [more] | VLD2010-101 CPSY2010-56 RECONF2010-70 pp.123-126 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
| RECONF | 2010-09-17 09:25 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | COGRE: A Novel Compact Logic Cell Architecture for Area Reduction Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-31 |
In order to implement logic functions, conventional field programmable gate arrays (FPGAs) adopt look-up tables (LUTs) a... [more] | RECONF2010-31 pp.79-84 |
| WBS, SAT (Joint) |
2010-06-10 13:25 |
Okinawa | Okinawa-ken-Seinen-Kaikan | Evaluation of an RF signal Direct-Processing Receiver for Reconfigurable Communication Equipment Midori Kato, Shiro Yoshikawa, Tamio Okui, Tetsuya Watanabe (NEC), Masayoshi Yoneda (NTSpace), Kenji Suzuki, Ryutaro Suzuki (NICT) SAT2010-2 |
This paper describes an evaluation of an RF signal Direct-Processing Receiver that samples the RF signal directly and ma... [more] | SAT2010-2 pp.7-10 |
| RECONF | 2010-05-13 14:55 |
Nagasaki | A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2010-4 |
Recently, since a mobile device is required to provide various functions, a lot of specialized hardware modules must be... [more] |
RECONF2010-4 pp.19-24 |
|
| RECONF | 2010-05-14 11:45 |
Nagasaki | Evaluation using Multiple Different Applications of OS for an FPGA-based Reconfigurable System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2010-14 |
Reconfigurable devices can be configured any logical hardware structures by users. Reconfigurable systems that have reco... [more] | RECONF2010-14 pp.75-80 |
|
| ED, SDM | 2010-02-23 11:00 |
Okinawa | Okinawaken-Seinen-Kaikan | Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network Yuta Shiratori, Kensuke Miura (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST) ED2009-208 SDM2009-205 |
We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon’s expansion of Boolean logic functio... [more] | ED2009-208 SDM2009-205 pp.71-76 |
| SCE | 2009-10-20 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Dynamically Reconfigurable Single Flux Quantum Logic Gates Yuki Yamanashi, Ichiro Okawa, Nobuyuki Yoshikawa (Yokohama Nat. Univ.) SCE2009-20 |
Novel reconfigurable superconductive single flux quantum logic gates, the function of which can be dynamically defined b... [more] | SCE2009-20 pp.19-23 |
| SR | 2009-07-30 16:20 |
Tokyo | Tokyo institute of technology | [Invited Talk]
RF CMOS Integrated Circuit
-- Reconfigurability and Scalability -- Kazuya Masu, Noboru Ishihara, Shuhei Amakawa (Tokyo Tech) SR2009-48 |
We discuss the issues of present and future RF CMOS integrated circuit, which is the most significant hardware component... [more] | SR2009-48 pp.165-166 |
| RECONF | 2009-05-14 13:30 |
Fukui | Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3 Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) RECONF2009-2 |
Dynamically Reconfigurable Processor Array(DRPA) has been received an attention as a flexible and power efficient off-lo... [more] | RECONF2009-2 pp.7-12 |
|
| SIS | 2009-03-05 15:45 |
Tokyo | [Special Talk]
System Realizations by Using Embedded Memories in FPGAs Yukihiro Iguchi (Meiji Univ.) |
FPGAs (Field Programmable Gate Arrays) have many embedded RAMs. We can use them for register files, FIFO (First In, Fi... [more] |
SIS2008-80 pp.49-54 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 15:10 |
Kanagawa | A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | VLD2008-121 CPSY2008-83 RECONF2008-85 pp.177-182 |
|
| CPSY | 2008-12-18 13:15 |
Kyoto | KYOTO Research Park | [Special Invited Talk]
An Introduction of Our Recent Research on VLIW from 3way to 9Nway Yasuhiko Nakashima (NAIST) CPSY2008-48 |
The first VLIW revealed as a hardware structure that could directly execute horizontal micro codes has been raised to on... [more] | CPSY2008-48 pp.31-36 |
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