| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-25 14:40 |
Online | Online | Parallelization and Vectorization of SpMM for Sparse Neural Network Yuta Tadokoro, Keiji Kimura, Hironori Kasahara (Waseda Univ.)  CPSY2020-55 DC2020-85 |
Pruning is one of the well-known model compression techniques in Deep Learning. Eliminating less important weights in th... [more] | CPSY2020-55 DC2020-85 pp.31-36 |
| IN, NS (Joint) |
2021-03-04 10:40 |
Online | Online | An Optimal Control Method for Multi-Job Rejection Rate in MEC Hajime Yuda, Yoshiaki Kitaguchi, Katsunori Yamaoka (Tokyo Tech) IN2020-66 |
In MEC, there is a possibility that the processing time will increase or the blocking rate of jobs in the edge server wi... [more] | IN2020-66 pp.73-78 |
| HWS, VLD [detail] | 2021-03-04 09:30 |
Online | Online | Design space exploration on low energy embedded multi-core processors Sayuri Onagi, Yuko Hara (Tokyo Tech) VLD2020-79 HWS2020-54 |
Nowadays, edge computing has been sought by increasing stream data and demand for real time processing so that distribut... [more] | VLD2020-79 HWS2020-54 pp.61-66 |
| EE | 2021-01-25 10:20 |
Online | Online (Zoom) | Online parameter identification for processor power estimation using performance monitoring information Shinichi Kawaguchi (KAIT) EE2020-26 |
The processor s of the computer in operation tends to be light load for long time . Therefore, it is required to improve... [more] | EE2020-26 pp.16-21 |
| PN | 2020-03-03 09:50 |
Kagoshima | (Cancelled but technical report was issued) |
DDoS defense method by logically isolating attackers Yutaka Nasu, Naoto Sumita, Masaki Murakami, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2019-63 |
In recent years, the number of DDoS occurrences and the traffic volume have increased, and attacks have resulted in the ... [more] | PN2019-63 pp.65-71 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Design and implementation of a RISC-V computer system running Linux in Verilog HDL Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech) VLD2019-72 CPSY2019-70 RECONF2019-62 |
RISC-V is an instruction set architecture developed at the University of California, Berkeley. Processors using RISC-V ... [more] |
VLD2019-72 CPSY2019-70 RECONF2019-62 pp.117-122 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 13:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Design and implementation of a RISC-V soft processor adopting five-stage pipelining Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech) VLD2019-73 CPSY2019-71 RECONF2019-63 |
In this paper, we propose a RISC-V soft processor adopting five-stage pipelining optimized for FPGAs that support RV32I,... [more] | VLD2019-73 CPSY2019-71 RECONF2019-63 pp.123-128 |
| PN | 2019-11-14 17:20 |
Kanagawa | Network-based DDoS prevention with newly developed Reconfigurable Communication Processors Naoto Sumita, Masaki Murakami, Yu Nishio, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2019-26 |
In order to cope with traffic growth and service diversity the Photonic Network Processor (PNP) has been proposed. As a ... [more] | PN2019-26 pp.15-22 |
|
| CPSY, DC, IPSJ-ARC [detail] | 2019-07-24 13:30 |
Hokkaido | Kitami Civic Hall | Proposal of Scalable Vector Instruction Set for Embedded RISC-V Processor Yoshiki Kimura, Tomoya Kikuchi, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) CPSY2019-18 DC2019-18 |
Recently, the use of FPGA in the embedded field has increased. However, development using FPGA is high development costs... [more] | CPSY2019-18 DC2019-18 pp.21-26 |
| RECONF | 2019-05-09 12:35 |
Tokyo | Tokyo Tech Front | Efficient Instruction Fetch Architectures for a RISC-V Soft Processor Hiromu Miyazaki, Junya Miura, Kenji Kise (Tokyo Tech) RECONF2019-1 |
We aim to develop a cost-effective RISC-V scalar processor of pipelining for FPGAs. In this report, we try to implement ... [more] | RECONF2019-1 pp.1-6 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-17 15:50 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | Real-Time Voltage and Frequency Scaling Scheme with IPC Controlling for SMT Processor Hiromi Suzuki, Yousuke Ide, Yuta Tsukahara, Nobuyuki Yamasaki (Keio Univ) CPSY2018-106 DC2018-88 |
In the field of Real-Time embedded systems, both of high-performance and low-power consumption are required. In this pap... [more] | CPSY2018-106 DC2018-88 pp.161-166 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-17 16:10 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | Design of Vector Unit for AI Acceleration in Embedded Processor Yosuke Ide, Hiromi Suzuki, Yuki Mori, Nobuyuki Yamasaki (Keio Univ.) CPSY2018-107 DC2018-89 |
In recent years, AI is applied in wide range of fields. Its learning and recognition are based on Neural Network (NN), w... [more] | CPSY2018-107 DC2018-89 pp.167-172 |
| SS | 2019-03-04 10:40 |
Okinawa | An improved LLF scheduling for reducing heap memory consumption in multiprocessor real-time system by considering laxity time Yuki Machigashira, Akio Nakata (Hirosima City Univ.) SS2018-55 |
Real-time embedded systems are often designed as multitasking systems in order to improve responsiveness to multiple ext... [more] | SS2018-55 pp.19-24 |
|
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-31 14:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Preliminary evaluation of special instruction implementation methods by high level synthesis Ryodai Iwamoto, Naoki Fujieda, Shuichi Ichikawa, Joji Sakamoto (TUT) VLD2018-88 CPSY2018-98 RECONF2018-62 |
Protection of intellectual properties and technical know-how is an important issue.In our previous work, we proposed imp... [more] | VLD2018-88 CPSY2018-98 RECONF2018-62 pp.101-106 |
| SCE | 2019-01-23 13:05 |
Tokyo | [Invited Talk]
Development of the single-flux-quantum signal processors for advancement of performance of the superconducting single photon detection systems Shigeyuki Miyajima, Masahiro Yabuno (NICT), Shigehito Miki (NICT/Kobe Univ.), Hirotaka Terai (NICT) SCE2018-29 |
We developed the advanced superconducting nanowire single photon detector (SSPD) systems with the single-flux-quantum (S... [more] | SCE2018-29 pp.23-28 |
|
| SCE | 2019-01-23 13:30 |
Tokyo | Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ) SCE2018-30 |
We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughp... [more] | SCE2018-30 pp.29-34 |
|
| SDM, ICD, ITE-IST [detail] | 2018-08-07 16:45 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | Power Consumption Estimation by Die Temperature for Processors Implemented on FPGA Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.) SDM2018-35 ICD2018-22 |
The importance of thermal management and temperature sensing is increasing for processors with power consumption lower t... [more] | SDM2018-35 ICD2018-22 pp.53-58 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-07-30 14:30 |
Kumamoto | Kumamoto City International Center | Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet Yosuke Yanai, Takeshi Matsuya, Yohei Kuga, Tokusashi Yuta, Jun Murai (Keio Univ.) CPSY2018-15 |
In this paper, we propose a processor with 1024 bit wide data path for packet processing. A software packet processing e... [more] | CPSY2018-15 pp.33-38 |
| ET | 2018-06-16 13:10 |
Aichi | Nanzan University | Educational Embedded System using Optical Transmisson of Virtual Machine Code Yosuke Senta (Kurume IT) ET2018-12 |
In one day college, it is more exciting to use actual robots or colorful led substrates in the programming practice. ... [more] |
ET2018-12 pp.1-6 |
| VLD, HWS (Joint) |
2018-02-28 15:25 |
Okinawa | Okinawa Seinen Kaikan | Architecture of Full-HD 60-fps Real-time Optical Flow Processor Satoshi Kanda (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-99 |
This paper describes the architecture design of Full-HD 60fps real-time optical flow processor. In this processor, the W... [more] | VLD2017-99 pp.61-66 |
[Return to Top Page]