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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD | 2024-01-29 17:00 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis
-- Toward comparative evaluation of latch-based and flip-flop-based circuits -- Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions)  VLD2023-90 RECONF2023-93 |
As a synchronous logic circuit, it is often argued that latch-based circuits are superior to flip-flop circuits in terms... [more] | VLD2023-90 RECONF2023-93 pp.59-64 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 09:55 |
Online | Online | Column-Parallel Pipelined ADC with Ring Amplifier for High Speed and High Spatial Resolution CMOS Image Sensor Takashi Kojima (TUS), Toshinori Otaka, Yusuke Kameda, Takayuki Hamamoto (TUS) VLD2020-28 ICD2020-48 DC2020-48 RECONF2020-47 |
CMOS image sensor that can capture images with both high time resolution and high spatial resolution is required for ins... [more] | VLD2020-28 ICD2020-48 DC2020-48 RECONF2020-47 pp.101-105 |
| SCE | 2019-01-23 13:30 |
Tokyo | Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ) SCE2018-30 |
We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughp... [more] | SCE2018-30 pp.29-34 |
|
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 10:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication Takashi Imagawa (Ritsumeikan Univ.), Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) VLD2017-45 DC2017-51 |
With the increase in the number of MIMO streams and OFDM subcarriers for high-speed wireless communication, the amount o... [more] | VLD2017-45 DC2017-51 pp.105-108 |
| SCE | 2017-08-09 14:35 |
Aichi | Nagoya Univ. (Higashiyama Campus) | Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.) SCE2017-17 |
We have started development of high-throughput rapid single-flux-quantum (RSFQ) microprocessors with the aim of higher p... [more] | SCE2017-17 pp.37-42 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Study about Optimization of Operational Amplifier for Gain Stages in the Pipeline ADC Daisuke Fujinami, Masahiro Sasaki (SIT) ICD2016-83 CPSY2016-89 |
A pipeline ADC (Analog to Digital Converter) comprises multiple stages connected by cascading whose main components are ... [more] | ICD2016-83 CPSY2016-89 p.93 |
| IT, ISEC, WBS | 2016-03-10 14:30 |
Tokyo | The University of Electro-Communications | A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) IT2015-116 ISEC2015-75 WBS2015-99 |
Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregat... [more] | IT2015-116 ISEC2015-75 WBS2015-99 pp.95-100 |
| SIS | 2014-03-06 11:40 |
Osaka | Gran Front Osaka, Knowledge Capital C-9F, 901 | Hardware Implementation of Soft Cascaded SVM Classifier Kazutaka Takeuchi, Jaehoon Yu (Osaka Univ.), Ryusuke Miyamoto (Meiji Univ.), Takao Onoye (Osaka Univ.) SIS2013-58 |
To speed up the object detection without degradation of the accuracy, the following two approaches are proposed: Reducin... [more] | SIS2013-58 pp.17-22 |
| SIS, IPSJ-AVM | 2012-09-20 10:40 |
Osaka | Tottori Pref. Osaka Office | A High-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard Wenjun Zhao, Takao Onoye (Osaka Univ.) SIS2012-18 |
This paper presents a hardware architecture of the transform applied in the emerging video coding standard-HEVC (High Ef... [more] | SIS2012-18 pp.11-16 |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
A study of a 1.5V operational cyclic current-mode ADC utilizing the pipeline conversion architecture Masatoshi Kamuro, Masanobu Ota, Yasuhiro Sugimoto (Chuo Univ.) ICD2011-115 |
In order to digitize the current signal, which flows through an inductor and changes a large amount depending on the loa... [more] | ICD2011-115 pp.71-74 |
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| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
High Linearity Open-loop Amplifier for Interpolated Pipeline ADC Yoshiyuki Hirooka, Hyunui Lee, Masaya Miyahara, Akira Matsuzawa (Titech) ICD2011-123 |
We propose the linearization technique of open-loop amplifier used in interpolated pipeline ADC. The A/D conversion sche... [more] | ICD2011-123 p.111 |
|
| CPM | 2009-08-11 13:55 |
Aomori | Hirosaki Univ. | FPGA implementation of a Wave-Pipelined Firewall Unit Keisuke Saito, Kei Ito, Shuya Imaruoka, Tomoaki Sato, Masa-aki Fukase (Hirosaki Univ.) CPM2009-48 |
We have been working on the development of H-HIPS by using a FPGA. A FPGA can change circuits information easily. But, i... [more] | CPM2009-48 pp.77-81 |
| NS, OCS, PN (Joint) |
2009-06-26 10:50 |
Nagasaki | Nagasaki Museum of History and Culture (Nagasaki) | Demonstration of 640Gbit/s (64 x 10Gbit/s) DWDM/NRZ-DPSK Optical Packet Switching Hideaki Furukawa, Naoya Wada, Tetsuya Miyazaki (NICT) PN2009-8 |
In this paper, in order to show the transparent operation of OPS systems, we introduce differential phase shift keying (... [more] | PN2009-8 pp.45-50 |
| VLD | 2009-03-11 14:25 |
Okinawa | Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) VLD2008-131 |
In this paper, a pipeline scheduling algorithm for minimizing total circuit area under throughput constraint is present... [more] |
VLD2008-131 pp.29-34 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 17:25 |
Kanagawa | A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-108 CPSY2008-70 RECONF2008-72 |
Small area, high performance and high productivity are required for application-specific processors in embedded systems.... [more] | VLD2008-108 CPSY2008-70 RECONF2008-72 pp.99-104 |
|
| PN, NS (Joint) |
2008-12-19 12:05 |
Hyogo | Koube Univ. | Development of 640 Gbit/s/port Optical Packet Switch Prototype Hideaki Furukawa, Naoya Wada, Hiroaki Harai, Naganori Takezawa (NICT), Keiichi Nashimoto (EpiPhotonics Corp.), Tetsuya Miyazaki (NICT) PN2008-41 |
We have developed 160 Gbit/s/port optical packet switch (OPS) prototype with optical label processing and optical buffer... [more] | PN2008-41 pp.53-58 |
| ICD, ITE-IST | 2008-10-23 14:10 |
Hokkaido | Hokkaido University | [Invited Talk]
Analog design isuues of high-resolution and low-power ADCs using a low voltage supply and sub-micron proceses Kunihiko Gotoh (FUJITSU LABORATORIES LTD.) ICD2008-76 |
The demand for high-speed (≧30 MS/s), high-resolution (≧10 bit) and low-power operation analog-to-digital converters (AD... [more] | ICD2008-76 pp.101-106 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | Comparison of Standard Cell Non-linear Asynchronous Pipelines Chammika Mannakkara, Tomohiro Yoneda (NII) VLD2007-78 DC2007-33 |
Two types of non-linear asynchronous pipeline constructs, namely Conditional Branch and Asynchronous were compared for 2... [more] | VLD2007-78 DC2007-33 pp.49-54 |
| ICD, ITE-IST | 2007-07-26 17:05 |
Hyogo | Low power consumption of H.264/AVC decoder with dynamic voltage and frequency scaling Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-52 |
We propose an elastic pipeline architecture that can apply dynamic voltage scaling (DVS) to a dedicated hardware, and ap... [more] | ICD2007-52 pp.89-94 |
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| ICD, ITE-IST | 2006-07-27 11:30 |
Shizuoka | A study on the multi-bit-pipelined A/D converter Hiroki Endou, Masaya Miyahara, Akira Matsuzawa (Titech) |
We have studied on the multi-bit pipeline A/D converter from the view pints of needed OP amp gain, needed capacitance, l... [more] | ICD2006-63 pp.17-22 |
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