| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
A study of a 1.5V operational cyclic current-mode ADC utilizing the pipeline conversion architecture Masatoshi Kamuro, Masanobu Ota, Yasuhiro Sugimoto (Chuo Univ.)  ICD2011-115 |
In order to digitize the current signal, which flows through an inductor and changes a large amount depending on the loa... [more] | ICD2011-115 pp.71-74 |
|
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
High Linearity Open-loop Amplifier for Interpolated Pipeline ADC Yoshiyuki Hirooka, Hyunui Lee, Masaya Miyahara, Akira Matsuzawa (Titech) ICD2011-123 |
We propose the linearization technique of open-loop amplifier used in interpolated pipeline ADC. The A/D conversion sche... [more] | ICD2011-123 p.111 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:50 |
Miyazaki | NewWelCity Miyazaki | Power Estimation of Variable Stages Pipeline Processor Using Power Gating Technique Masaki Tanaka, Takahiro Sasaki, Tomoyuki Nakabayashi, Kazuhiko Ohno, Toshio Kondo (Mie Univ) CPSY2011-45 |
Recently, the increase of an energy consumption of mobile computers caused by performance enhancement becomes one seriou... [more] | CPSY2011-45 pp.15-20 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2011-03-19 14:45 |
Okinawa | Parallel C code generation from Simulink models Takahiro Kumura (NEC/Osaka Univ.), Masato Edahiro, Yuichi Nakamura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) CPSY2010-80 DC2010-79 |
This paper proposes a method to generate parallel C code from models developed on the Simulink which is a model-based ... [more] |
CPSY2010-80 DC2010-79 pp.303-308 |
|
| SR | 2011-01-28 14:15 |
Fukuoka | Kyushu Institute of Technology | 1GS/s Current Mode Pipeline ADC in 90nm CMOS Kei Ando, Takashi Nozawa, Ta Tuan Thanh, Shoichi Tanifuji, Suguru Kameda, Noriharu Suematsu, Tadashi Takagi, Kazuo Tsubouchi (Tohoku Univ.) SR2010-83 |
In heterogeneous wireless network, multimode tranceiver for various wireless system is needed. We have already proposed... [more] |
SR2010-83 pp.89-94 |
| ICD, SDM | 2010-08-26 11:25 |
Hokkaido | Sapporo Center for Gender Equality | 10bit-300MHz Double-Sampling Pipelined ADC with Digital Calibration for Memory Effects Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho (Panasonic) SDM2010-129 ICD2010-44 |
This paper describes an on-chip digital calibration technique to eliminate a memory effect error in Double-sampling Pipe... [more] | SDM2010-129 ICD2010-44 pp.29-34 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | High Performance Hybrid Wave-Pipelined Adder Using A Gain Based Delay Model Truong Thi Kim Tuoi, Jubee Tada, Gensuke Goto (Yamagata Univ.) |
This paper describes a hybrid wave-pipelined adder using a gain based delay model in order to balance the delays in a co... [more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Review of design methodology for pipelined CPU. Case study: trade-off between pipelined and non-pipelined Little Computer 3 Bui Minh Thanh, Hoang Trang, Ho Trung My (HCMUT) |
The review of design methodology for pipelined CPU is presented in this paper. Thanks to high performance, the piplined ... [more] | |
| IT, ISEC, WBS | 2010-03-05 10:50 |
Nagano | Nagano-Engineering Campus, Shinshu University | Discussion on a self-calibrated pipeline A/D converter. Tohru Kohda, Masatora Ogata (Kyushu Univ.) IT2009-119 ISEC2009-127 WBS2009-98 |
A class of pipelined A/D converters in one of the A/D converter has recently been proposed. We study pipeline A/D conver... [more] | IT2009-119 ISEC2009-127 WBS2009-98 pp.313-318 |
| IT, ISEC, WBS | 2010-03-05 13:25 |
Nagano | Nagano-Engineering Campus, Shinshu University | Behavior Level Design of Turbo TCM Decoder
-- Automatic Synthesis of Pipeline Processing Circuit and Comparison of RTL Design -- Hayato Taira, Haruo Ogiwara (Nagaoka Univ. of Tech.) IT2009-122 ISEC2009-130 WBS2009-101 |
This paper shows a turbo TCM (Trellis Coded Modulation) hardware decoder design with a pipeline processing circuit using... [more] | IT2009-122 ISEC2009-130 WBS2009-101 pp.331-335 |
| SIP, CAS, CS | 2010-03-02 13:45 |
Okinawa | Hotel Breeze Bay Marina, Miyakojima | [Poster Presentation]
Low Power Processor Architecture based on a Dynamic Reconfigurable Scheme in Pipeline Stages Masashi Ohki, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-120 SIP2009-165 CS2009-115 |
A processor architecture which can execute instructions in dynamic reconfigurable pipeline manner is proposed. By help o... [more] | CAS2009-120 SIP2009-165 CS2009-115 pp.237-238 |
| AP | 2010-02-18 11:40 |
Tokyo | Toshiba | Acceleration of FDTD Method with the Time and Space Pipeline on the Cell.B.E. Sho Endo, Jun Sonoda (Sendai Nat Coll. of Tech.), Motoyuki Sato (Tohoku Uni.) AP2009-190 |
Nowadays FDTD method have been accelerated with Cell Broadband Engine (Cell/B.E.) However there have been a problem that... [more] | AP2009-190 pp.35-40 |
| SCE | 2009-10-20 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Logic Design Verification Method for SFQ Circuits Considering Pipeline Processing Behavior Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ) SCE2009-17 |
We propose a verification method of pipeline processing behavior of SFQ circuits. SFQ logic circuits work synchronously ... [more] | SCE2009-17 pp.1-6 |
| CPM | 2009-08-11 13:55 |
Aomori | Hirosaki Univ. | FPGA implementation of a Wave-Pipelined Firewall Unit Keisuke Saito, Kei Ito, Shuya Imaruoka, Tomoaki Sato, Masa-aki Fukase (Hirosaki Univ.) CPM2009-48 |
We have been working on the development of H-HIPS by using a FPGA. A FPGA can change circuits information easily. But, i... [more] | CPM2009-48 pp.77-81 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | Pipelined Multithreading with Clustered Communication on Commodity Multi-Core Processors *Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-26 |
Recently proposed pipelined multithreading (PMT) techniques have shown great applicability to parallelizing general prog... [more] | CPSY2009-26 pp.97-102 |
|
| NS, OCS, PN (Joint) |
2009-06-26 10:50 |
Nagasaki | Nagasaki Museum of History and Culture (Nagasaki) | Demonstration of 640Gbit/s (64 x 10Gbit/s) DWDM/NRZ-DPSK Optical Packet Switching Hideaki Furukawa, Naoya Wada, Tetsuya Miyazaki (NICT) PN2009-8 |
In this paper, in order to show the transparent operation of OPS systems, we introduce differential phase shift keying (... [more] | PN2009-8 pp.45-50 |
| VLD | 2009-03-11 14:25 |
Okinawa | Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) VLD2008-131 |
In this paper, a pipeline scheduling algorithm for minimizing total circuit area under throughput constraint is present... [more] |
VLD2008-131 pp.29-34 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 17:25 |
Kanagawa | A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-108 CPSY2008-70 RECONF2008-72 |
Small area, high performance and high productivity are required for application-specific processors in embedded systems.... [more] | VLD2008-108 CPSY2008-70 RECONF2008-72 pp.99-104 |
|
| PN, NS (Joint) |
2008-12-19 12:05 |
Hyogo | Koube Univ. | Development of 640 Gbit/s/port Optical Packet Switch Prototype Hideaki Furukawa, Naoya Wada, Hiroaki Harai, Naganori Takezawa (NICT), Keiichi Nashimoto (EpiPhotonics Corp.), Tetsuya Miyazaki (NICT) PN2008-41 |
We have developed 160 Gbit/s/port optical packet switch (OPS) prototype with optical label processing and optical buffer... [more] | PN2008-41 pp.53-58 |
| CPSY | 2008-10-31 15:00 |
Hiroshima | Hiroshima City Univ. | Development of Improved Variable Stages Pipeline Architecture and its LSI Design Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ) CPSY2008-34 |
Recently, the increase of the energy consumption of mobile computers caused by performance enhancement becomes one ser... [more] |
CPSY2008-34 pp.29-34 |
[Return to Top Page]