Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, VLD |
2024-01-29 17:00 |
Kanagawa |
AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis
-- Toward comparative evaluation of latch-based and flip-flop-based circuits -- Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-90 RECONF2023-93 |
As a synchronous logic circuit, it is often argued that latch-based circuits are superior to flip-flop circuits in terms... [more] |
VLD2023-90 RECONF2023-93 pp.59-64 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 09:55 |
Online |
Online |
Column-Parallel Pipelined ADC with Ring Amplifier for High Speed and High Spatial Resolution CMOS Image Sensor Takashi Kojima (TUS), Toshinori Otaka, Yusuke Kameda, Takayuki Hamamoto (TUS) VLD2020-28 ICD2020-48 DC2020-48 RECONF2020-47 |
CMOS image sensor that can capture images with both high time resolution and high spatial resolution is required for ins... [more] |
VLD2020-28 ICD2020-48 DC2020-48 RECONF2020-47 pp.101-105 |
ICD, HWS [detail] |
2020-10-26 09:25 |
Online |
Online |
Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2020-26 ICD2020-15 |
To reduce the latency of pairing calculation for advanced cryptography, hardware implementations with pipelined modular ... [more] |
HWS2020-26 ICD2020-15 pp.7-12 |
MW (2nd) |
2020-05-13 - 2020-05-15 |
Overseas |
CU, Bangkok, Thailand (Postponed) |
Development of Rectifiers for Wireless Power Transfer to Pipeline Inspection Robots Koki Miwatashi, Naoki Shinohara, Tomohiko Mitani (Kyoto Univ.) |
A novel method of pipeline inspection from inside by robots has been used, and has some problems. One is a limited dista... [more] |
|
ICTSSL, CAS |
2020-01-30 18:00 |
Tokyo |
|
High-level synthesis oriented histogram series duplication for overlapping continuous image processing Moena Yamasaki, Akira Yamawaki (Kyutech) CAS2019-80 ICTSSL2019-49 |
In order to quickly realize a high-performance and power-saving embedded image processing device, it is effective to use... [more] |
CAS2019-80 ICTSSL2019-49 pp.85-89 |
PEM (Workshop) |
2019-11-18 - 2019-11-19 |
Mie |
Sinfonia Technology Hibiki Hall Ise (Ise Tourism and Culture Hall) |
Time-domain Analysis of Microwave Guided-Modes Propagating along FRPM Pipe Wall for Pipeline Inspection Sayaka Matsukawa (AIST), Kosuke Yoshida (Mie Univ.), Tadahiro Okuda, Masaya Hazama (Kurimoto Ltd,), Satoru Kurokawa (AIST), Hiroshi Murata (Mie Univ.) |
We have proposed a new nondestructive inspection technique for underground FRPM pipelines by using microwave guided-mode... [more] |
|
PEM (Workshop) |
2019-11-18 - 2019-11-19 |
Mie |
Sinfonia Technology Hibiki Hall Ise (Ise Tourism and Culture Hall) |
Time Domain Analysis of Reflected Microwave Signal for FRPM Pipeline Inspection to Detect Foreign Objects Kousuke Yoshida (Mie Univ.), Sayaka Matsukawa (AIST), Yoshihiro Nishimura (Mie Univ.), Satoru Kurokawa (AIST), Tadahiro Okuda, Masaya Hazama (Kurimoto Ltd.), Hiroshi Murata (Mie Univ.) |
We have proposed a new non-destructive inspection method for FRPM (Fiberglass Reinforced Plastics Mortar) pipelines usin... [more] |
|
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] |
2019-07-23 14:25 |
Kochi |
Kochi University of Technology |
Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 |
Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed ... [more] |
ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 pp.151-156 |
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] |
2019-07-23 14:50 |
Kochi |
Kochi University of Technology |
An FPGA Implementation of Aggregate Signature Schemes with Pipelined Modular Multiplier Yota Okuaki, Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33 |
Expectations for "Advanced Cryptography" are increasing in order to enhance the security of cyber physical systems and c... [more] |
ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33 pp.157-162 |
SCE |
2019-01-23 13:30 |
Tokyo |
|
Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ) SCE2018-30 |
We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughp... [more] |
SCE2018-30 pp.29-34 |
HWS, ICD |
2018-10-29 14:30 |
Osaka |
Kobe Univ. Umeda Intelligent Laboratory |
An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) HWS2018-50 ICD2018-42 |
One of the biggest problems of the emerging cyber-physical and cloud computing systems is how to ensure security with en... [more] |
HWS2018-50 ICD2018-42 pp.19-24 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 10:55 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication Takashi Imagawa (Ritsumeikan Univ.), Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) VLD2017-45 DC2017-51 |
With the increase in the number of MIMO streams and OFDM subcarriers for high-speed wireless communication, the amount o... [more] |
VLD2017-45 DC2017-51 pp.105-108 |
SCE |
2017-08-09 14:35 |
Aichi |
Nagoya Univ. (Higashiyama Campus) |
Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.) SCE2017-17 |
We have started development of high-throughput rapid single-flux-quantum (RSFQ) microprocessors with the aim of higher p... [more] |
SCE2017-17 pp.37-42 |
ICD, CPSY |
2016-12-15 15:30 |
Tokyo |
Tokyo Institute of Technology |
[Poster Presentation]
Study about Optimization of Operational Amplifier for Gain Stages in the Pipeline ADC Daisuke Fujinami, Masahiro Sasaki (SIT) ICD2016-83 CPSY2016-89 |
A pipeline ADC (Analog to Digital Converter) comprises multiple stages connected by cascading whose main components are ... [more] |
ICD2016-83 CPSY2016-89 p.93 |
ICD, CPSY |
2016-12-16 14:20 |
Tokyo |
Tokyo Institute of Technology |
[Invited Talk]
A Data-Driven Processor Realizing Trillion Sensors Universe Hiroaki Nishikawa (Univ. of Tsukuba) ICD2016-96 CPSY2016-102 |
This paper introduces a data-driven processor aiming at realizing Trillion Sensors Universe. Execution control scheme in... [more] |
ICD2016-96 CPSY2016-102 pp.139-144 |
IA |
2016-11-04 10:55 |
Overseas |
Taipei (Taiwan) |
Real-time Abnormal Traffic Detection Circuit Based on Simple Frequent-Itemset-Mining Method Shuji Sannomiya, Akira Sato, Kenichi Yoshida (Univ. of Tsukuba) IA2016-47 |
To resist the growth of abnormal traffic such as P2P flows, DDoS attacks and Internet worms, a circuit design to realize... [more] |
IA2016-47 pp.93-98 |
IT, ISEC, WBS |
2016-03-10 14:30 |
Tokyo |
The University of Electro-Communications |
A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) IT2015-116 ISEC2015-75 WBS2015-99 |
Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregat... [more] |
IT2015-116 ISEC2015-75 WBS2015-99 pp.95-100 |
NS, RCS (Joint) |
2015-12-18 11:25 |
Ehime |
Matsuyama Community Center |
BER/PER Simulation on Fractional bit width and Circuit Design of FFT for IEEE802.11ah Soichiro Kanagawa (NAIST), Nguyen Dang Hai (DUT), Hong Thi Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) RCS2015-258 |
In recent years, the concept of IoT has attracted attention. It utilize the data obtained by connecting the things to th... [more] |
RCS2015-258 pp.87-92 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 13:45 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
Fast and Accurate Estimation of Execution Cycles for ARM Architecture Go Sato, Yuki Ando, Hiroaki Takada, Shinya Honda, Yutaka Matsubara (Nagoya Univ) VLD2015-73 DC2015-69 |
(To be available after the conference date) [more] |
VLD2015-73 DC2015-69 pp.231-236 |
SAT |
2015-10-07 09:10 |
Osaka |
Osaka University Nakanoshima Center |
A system performance study on reducing power consumption of DBF/channelizer for communication satellite Teruaki Orikasa, Amane Miura (NICT), Naoki Kobayashi (NEC Space Technologies), Shinji Senba (AXIS) SAT2015-26 |
We have been researching and developing a digital Beam Former and Digital Channelizer (DBF/channelizer) for communicatio... [more] |
SAT2015-26 pp.1-6 |