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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICM, NS, CQ, NV (Joint) |
2023-11-22 09:00 |
Ehime | Ehime Prefecture Gender Equality Center (Primary: On-site, Secondary: Online) |
Evaluation of Improvement Plans to Increase the Efficiency of Performance Data Transfer for Server Systems Chika Iiyama (Ocha Univ.), Akira Hirai, Mari Yamaoka, Naoto Fukumoto (Fujitsu), Masato Oguchi (Ocha Univ.)  NS2023-117 |
In recent years, demand for shared use of multiple servers has been increasing. In order to perform load balancing on th... [more] | NS2023-117 pp.38-43 |
| RECONF | 2023-06-08 16:00 |
Kochi | Eikokuji Campus, Kochi University of Technology (Primary: On-site, Secondary: Online) |
Parallelization of Prim's Algorithm Using FPGA and Its Performance Evaluation Noritsune O, Kenji Kanazawa, Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2023-3 |
A subgraph of an undirected graph G that is connected and contains no closed paths is called a tree, a global tree is a ... [more] | RECONF2023-3 pp.13-16 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2023-03-23 16:25 |
Kagoshima | Amagi Town Disaster Prevention Center (Tokunoshima) (Primary: On-site, Secondary: Online) |
Evaluation of Bit-Reduced Homomorphic Encryption Library on Intel Xeon and Fujitsu A64FX Masaki Nishi, Teppei Shishido, Xinyi Li, Keiji Kimura (Waseda Univ.), Kentaro Sano (RIKEN) CPSY2022-38 DC2022-97 |
As deep learning is used in various applications, the protection of training data, input data, inference results, and tr... [more] | CPSY2022-38 DC2022-97 pp.25-30 |
| SR | 2022-05-12 10:30 |
Tokyo | NICT Koganei (Primary: On-site, Secondary: Online) |
Parallelization and Time Division Multiplexing for 1-bit Bandpass Delta-Sigma Modulator Takashi Maehata (SEI), Noriharu Suematsu (Tohoku University) SR2022-5 |
The 1-bit bandpass delta-sigma modulator (1-bit BP-DSM) outputs RF signals directly from the digital part without using ... [more] | SR2022-5 pp.19-26 |
| IN, NS (Joint) |
2021-03-04 10:10 |
Online | Online | A Study on Spraying Heavy Hitters for Fast Stateful Packet Processing in Multi-threaded NDN Software Routers Junji Takemasa (Osaka Univ.), Atsushi Tagami (KDDI Research, Inc.), Yuki Koizumi, Toru Hasegawa (Osaka Univ.) IN2020-61 |
In Named Data Networking (NDN), a request packet is forwarded according to a content name, and the corresponding respons... [more] | IN2020-61 pp.43-48 |
| ICD, CPSY, CAS | 2018-12-21 16:00 |
Okinawa | Accelerating the Held-Karp Algorithm for the symmetric traveling salesman problem Kazuro Kimura, Shinya Higa, Masao Okita, Fumihiko Ino (Osaka Univ.) CAS2018-84 ICD2018-68 CPSY2018-50 |
In this paper, we propose an acceleration method for the Held-Karp algorithm that solves the symmetric traveling salesma... [more] | CAS2018-84 ICD2018-68 CPSY2018-50 pp.31-36 |
|
| CPSY, DC, IPSJ-ARC [detail] | 2018-06-15 13:10 |
Yamagata | Takamiya Rurikura Resort | Implementation of Code Generation for Parallel Processing Based on Parallelization Directives in LLVM IR Code Kengo Jingu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2018-6 DC2018-6 |
Nowadays, multi-core processors are widely used, and the speedup can be accomplished by thread-level parallel processing... [more] | CPSY2018-6 DC2018-6 pp.107-112 |
| VLD, HWS (Joint) |
2018-03-01 14:55 |
Okinawa | Okinawa Seinen Kaikan | Core allocation with mixed multirate tasks in model-based parallelization Yoshihiro Ikeda, Masato Edahiro (Nagoya Univ) VLD2017-114 |
In recent embedded systems, multi-core processors and parallel programming are introduced to improve performance.Also, l... [more] | VLD2017-114 pp.151-156 |
| VLD, HWS (Joint) |
2018-03-01 15:20 |
Okinawa | Okinawa Seinen Kaikan | Hardware/Software co-design environment in model-based parallelization (MBP) Kazuki Kashiwabara, Shinya Honda, Masato Edahiro (Nagoya Univ.) VLD2017-115 |
In recent years, while the complexity and high performance of in-vehicle systems are progressing, restrictions on time a... [more] | VLD2017-115 pp.157-162 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-38 DC2017-44 |
This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-sw... [more] | VLD2017-38 DC2017-44 pp.67-72 |
| PRMU | 2017-10-13 10:40 |
Kumamoto | Parallelization of the structure of neural network for super-resolution Kenta Tanaka, Yasukuni Mori (Chiba Univ.) PRMU2017-89 |
Super-resolution is a technique of outputting the high-resolution image for an image with low resolution. In this paper... [more] |
PRMU2017-89 pp.149-154 |
|
| CS, CQ, NV (Joint) |
2016-04-21 10:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Parallel Implementation of Cipher on CPU/GPU for Programmable Optical Access Equipment Takahiro Suzuki, Sang-Yuep Kim, Jun-ichi Kani, Ken-Ichi Suzuki, Akihiro Otaka (NTT) CS2016-1 |
Recently, NFV and SDN are attracting attention with the goal being enhanced networks efficiency. In access network, soft... [more] | CS2016-1 pp.1-6 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-05 14:30 |
Oita | B-Con Plaza (Beppu) | Efficient Thread Control Method for Parallel Loop Processing by Dynamic Binary Translation Hiroyuki Obuchi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2015-29 |
In order to effectively utilize the performance of multicore processors spreading commonly at present, it is an importan... [more] | CPSY2015-29 pp.155-160 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 13:40 |
Kanagawa | Hiyoshi Campus, Keio University | Relaxing constraint conditions in parallelizing compiler based on a polyhedral model Toma Ogata, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) VLD2014-142 CPSY2014-151 RECONF2014-75 |
Recently, it is general that computer has more than one processor inside and it is important to parallelize program to ... [more] | VLD2014-142 CPSY2014-151 RECONF2014-75 pp.187-192 |
| CPSY, DC (Joint) |
2014-07-30 17:00 |
Niigata | Toki Messe, Niigata | Content-Aware Resolution Management and Auto-Parallelization for a Video Processing Library Masahiro Mizuno, Takuya Matsunaga, Tomoaki Tsumura, Hiroshi Matsuo (Nagoya Inst. of Tech.) CPSY2014-43 |
The performance of general purpose computers is increasing rapidly, and now they are capable of running video processing... [more] | CPSY2014-43 pp.197-202 |
| AP | 2014-06-12 12:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Parallelization of FDTD and its open source program Akio Oga (EEM Inc.) AP2014-41 |
Several techniques parallelizing FDTD are presented. They include OpenMP, Multi-threading, MPI, CUDA and OpenCL. Program... [more] | AP2014-41 pp.7-12 |
| SIS | 2014-03-06 11:40 |
Osaka | Gran Front Osaka, Knowledge Capital C-9F, 901 | Hardware Implementation of Soft Cascaded SVM Classifier Kazutaka Takeuchi, Jaehoon Yu (Osaka Univ.), Ryusuke Miyamoto (Meiji Univ.), Takao Onoye (Osaka Univ.) SIS2013-58 |
To speed up the object detection without degradation of the accuracy, the following two approaches are proposed: Reducin... [more] | SIS2013-58 pp.17-22 |
| DC, CPSY (Joint) |
2013-08-02 14:30 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Reduction of Runtime Overhead in Automated Parallel Processing System using Valgrind Takayuki Hoshi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) CPSY2013-23 |
In order to efficiently utilize the performance of multicore processors, thread level parallel processing is indispensab... [more] | CPSY2013-23 pp.79-84 |
| DC, CPSY (Joint) |
2012-08-02 18:00 |
Tottori | Torigin Bunka Kaikan | An Automatic Device Memory Allocation Method for OpenMPC Hiroaki Uchiyama, Tomoaki Tsumura, Hiroshi Matsuo (Nagoya Inst. of Tech.) CPSY2012-17 |
The CUDA programming model provides better abstraction for GPU programming. However, it is still hard to build program b... [more] | CPSY2012-17 pp.49-54 |
| VLD | 2012-03-06 15:30 |
Oita | B-con Plaza | CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-129 |
In recent years, circuit design in languages with higher abstraction level has been widely noticed to address the proble... [more] | VLD2011-129 pp.55-60 |
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