|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM, ICD, ITE-IST [detail] |
2017-08-01 09:45 |
Hokkaido |
Hokkaido-Univ. Multimedia Education Bldg. |
Parallel Programming of Non-volatile Power-up States of SRAM Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya (Univ. of Tokyo), Hirofumi Shinohara (Waseda Univ.), Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2017-38 ICD2017-26 |
A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Paralle... [more] |
SDM2017-38 ICD2017-26 pp.49-54 |
ICD |
2008-04-18 10:00 |
Tokyo |
|
A 65nm Pure CMOS One-time Programmable Memory Using a Two-Port Antifuse Cell Implemented in a Matrix Structure Kensuke Matsufuji, Toshimasa Namekawa, Hiroaki Nakano, Hiroshi Ito, Osamu Wada, Nobuaki Otsuka (Toshiba) ICD2008-8 |
A Pure CMOS One-time Programmable(PCOP)memory using an antifuse is presented. PCOP memory adopts two-port cell architect... [more] |
ICD2008-8 pp.39-44 |
|
|
|
Copyright and reproduction :
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
|
[Return to Top Page]
[Return to IEICE Web Page]
|