Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, HWS, ICD |
2024-03-01 11:15 |
Okinawa |
(Primary: On-site, Secondary: Online) |
Investigation of electromagnetic irradiation noise reduction by on-chip LDOs Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.) VLD2023-124 HWS2023-84 ICD2023-113 |
IC chips are subject to the threat of fault injection attacks, which cause circuit malfunctions (faults) by injecting il... [more] |
VLD2023-124 HWS2023-84 ICD2023-113 pp.131-134 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-29 15:05 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
Evaluation of power delivery networks in secure semiconductor systems Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Makoto Nagata (Kobe Univ.) VLD2022-33 ICD2022-50 DC2022-49 RECONF2022-56 |
With the development of the IoT, hardware security is becoming increasingly important. Physical attacks on cryptoprocess... [more] |
VLD2022-33 ICD2022-50 DC2022-49 RECONF2022-56 pp.82-86 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 14:20 |
Online |
Online |
A Dual-mode SAR ADC to Detect Power Analysis Attack Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.) VLD2021-30 ICD2021-40 DC2021-36 RECONF2021-38 |
Distributed IoT devices are exposed to unexpected interferences by physical accesses by malicious attackers. An on-chip ... [more] |
VLD2021-30 ICD2021-40 DC2021-36 RECONF2021-38 pp.78-82 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 14:45 |
Online |
Online |
Diagnosis of Switching-Induced IR Drop by On-Chip Voltage Monitors Kazuki (Kobe Univ.), Leonidas Kataselas (Aristotle Univ.), Ferenc Fodor (IMEC), Alkis Hatzopoulos (Aristotle Univ.), Makoto Nagata (Kobe Univ.), Erik Jan Marinissen (IMEC) VLD2021-31 ICD2021-41 DC2021-37 RECONF2021-39 |
On-chip monitor (OCM) circuits enable us to observe dynamic power-supply (PS) waveforms within power domains individuall... [more] |
VLD2021-31 ICD2021-41 DC2021-37 RECONF2021-39 pp.83-86 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 14:25 |
Online |
Online |
On-chip power supply noise monitoring for evaluation of multi-chip board power delivery networks Daichi Nakagawa, Kazuki Yasuda, Masaru Mashiba, Kazuki Monta, Takaaki Okidono, Takuji Miki, Makoto Nagata (Kobe Univ) VLD2020-31 ICD2020-51 DC2020-51 RECONF2020-50 |
In these days, information and communication technology has been evolving more and more, and hardware security has been ... [more] |
VLD2020-31 ICD2020-51 DC2020-51 RECONF2020-50 pp.115-117 |
SDM, ICD, ITE-IST [detail] |
2019-08-09 12:00 |
Hokkaido |
Hokkaido Univ., Graduate School /Faculty of Information Science and |
Evaluation of IC-Chip Noise Reduction using Magnetic Materials Kosuke Jike, Koh Watanabe, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata (Kobe Univ), Akihiro Takahashi, Yasunori Miyazawa, Masahiro Yamaguchi (Tohoku Univ) SDM2019-49 ICD2019-14 |
Suppression of noise emitted from digital integrated circuit (IC) chip is expected by using magnetic materials. The freq... [more] |
SDM2019-49 ICD2019-14 pp.79-83 |
EMCJ, IEE-EMC |
2014-06-20 10:35 |
Hyogo |
Kobe Univ. |
Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata (Kobe Univ.), Yu-ichi Hayashi, Naofumi Homma (Tohoku Univ.), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech) EMCJ2014-10 |
Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths... [more] |
EMCJ2014-10 pp.1-6 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 15:40 |
Kanagawa |
Hiyoshi Campus, Keio University |
Methodology for NBTI measurement using an on-chip leakage monitor circuit Takaaki Sato, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2013-131 CPSY2013-102 RECONF2013-85 |
Miniaturization in recent years ,LSI's aging has become prominent as a factor that prevents the normal operation.By meas... [more] |
VLD2013-131 CPSY2013-102 RECONF2013-85 pp.173-178 |
SDM, ICD |
2013-08-01 13:45 |
Ishikawa |
Kanazawa University |
[Invited Talk]
Design and diagnosis of 100GB/s Wide I/O with 4096b TSVs through Active Silicon Interposer Makoto Nagata, Satoshi Takaya (Kobe Univ.), Hiroaki Ikeda (ASET) SDM2013-71 ICD2013-53 |
A 4096-bit wide I/O bus structure is designed and demonstrated with a three dimensional chip stack incorporating memory,... [more] |
SDM2013-71 ICD2013-53 pp.31-34 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 16:00 |
Kanagawa |
|
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72 |
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] |
VLD2012-118 CPSY2012-67 RECONF2012-72 pp.63-68 |
ICD, SDM |
2012-08-02 14:40 |
Hokkaido |
Sapporo Center for Gender Equality, Sapporo, Hokkaido |
Intra/Inter Tier Substrate Noise Measurements in 3D ICs Yasumasa Takagi, Yuuki Araga, Makoto Nagata (Kobe Univ.), Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Julien Ryckaert, Eric Beyne (IMEC) SDM2012-72 ICD2012-40 |
Substrate noise propagation among stacked dice is evaluated in a 3D test vehicle of 2 tier stacking. Each tier incorpora... [more] |
SDM2012-72 ICD2012-40 pp.49-54 |
ICD |
2011-12-16 15:25 |
Osaka |
|
[Invited Talk]
Power Noise in VLSI Chip
-- from Silicon Substrate to Electromagnetic Environment -- Makoto Nagata (Kobe Univ.) ICD2011-131 |
Power noise of VLSI chips will be discussed, in terms of chip-package-board concurrent and integrated analysis as well a... [more] |
ICD2011-131 pp.143-148 |
ICD, ITE-IST |
2011-07-22 09:25 |
Hiroshima |
Hiroshima Institute of Technology |
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator Tetsuya Iizuka, Kunihiro Asada (Univ. of Tokyo) ICD2011-26 |
This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring o... [more] |
ICD2011-26 pp.63-68 |
ICD, ITE-IST |
2011-07-22 10:25 |
Hiroshima |
Hiroshima Institute of Technology |
Analysis Methods of Substrate Sensitivity in an Analog Circiut Satoshi Takaya, Yoji Bando (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2011-28 |
Substrate noise sensitivity of an analog circuit consists of the sensitivity of a device and noise propagation from the ... [more] |
ICD2011-28 pp.73-78 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 11:20 |
Fukuoka |
Kyushu University |
A Consideration of Substrate Noise Sensitivity of Analog Elements Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) CPM2010-126 ICD2010-85 |
Measure substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 32 different geometor... [more] |
CPM2010-126 ICD2010-85 pp.13-17 |
ICD, ITE-IST |
2010-07-22 09:30 |
Osaka |
Josho Gakuen Osaka Center |
On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration Takushi Hashida, Hiroshi Matsumoto, Makoto Nagata (Kobe Univ.) ICD2010-21 |
On-chip waveform capture exhibits the resolution of 10 ps and 200 uV with 1024 steps, and SFDR of 63.2dB in 700-MHz sign... [more] |
ICD2010-21 pp.1-4 |
ICD, ITE-IST |
2010-07-22 10:45 |
Osaka |
Josho Gakuen Osaka Center |
Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) ICD2010-24 |
In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse co... [more] |
ICD2010-24 pp.15-20 |
ICD, ITE-IST |
2009-10-01 10:00 |
Tokyo |
CIC Tokyo (Tamachi) |
Evaluation and Analysis of Substrate Noise in Microprocessor Yoji Bando (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Goichi Yokomizo, Kunihiko Tsuboi (STARC), Ying Shiun Li, Shen Lin (Apache), Makoto Nagata (Kobe Univ./A-R-Tec) ICD2009-35 |
An integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through... [more] |
ICD2009-35 pp.11-14 |
ICD, ITE-IST |
2009-10-01 10:25 |
Tokyo |
CIC Tokyo (Tamachi) |
Chip-to-Chip Half Duplex Data Communication at 135 Mbps Over Power-Supply Rails Takushi Hashida, Makoto Nagata (Kobe Univ.) ICD2009-36 |
Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, packa... [more] |
ICD2009-36 pp.15-18 |
ICD |
2008-12-11 13:30 |
Tokyo |
Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan |
[Poster Presentation]
Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring Yuuki Araga, Takushi Hashida, Makoto Nagata (Kobe Univ.) ICD2008-108 |
Multi-channel waveform monitoring system for large-scale SoCs.
The system consists of probing front end circuits and a ... [more] |
ICD2008-108 pp.39-42 |