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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 11:00 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)  CPSY2022-3 DC2022-3 |
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] | CPSY2022-3 DC2022-3 pp.13-18 |
| IN, RCS, NV (Joint) |
2022-05-26 15:45 |
Kanagawa | Keio University (Hiyoshi Campus) (Primary: On-site, Secondary: Online) |
[Tutorial Lecture]
Distributed Lossy Multi-terminal Communications over Fading MAC and Decision Making (This tutorial is funded by IoTAD-CEO project under CominLab) Tad Matsumoto (IMT-Atlantique, Brest, France/Professor Emeritus, JAIST), Elsa Dupraz (IMT-Atlantique, Brest, France) RCS2022-18 |
Network Information Theory is an extension of Shannon’s Information Theory to Networks. We believe that the key to the s... [more] | RCS2022-18 pp.26-27 |
| DC | 2021-12-10 13:00 |
Kagawa | (Primary: On-site, Secondary: Online) |
A Low Power Oriented Multiple Target Test Generation Method Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55 |
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] | DC2021-55 pp.1-6 |
| DC | 2021-02-05 14:00 |
Online | Online | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 15:45 |
Online | Online | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12 |
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] | CPSY2020-12 DC2020-12 pp.75-80 |
| VLD | 2013-03-04 13:50 |
Okinawa | Okinawa Seinen Kaikan | A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application Junpei Kamei, Shingo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-136 |
In error tolerant applications, some specific errors, which are of certain types or have severities within certain limit... [more] | VLD2012-136 pp.1-6 |
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