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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
15:45		 Online Online A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns
Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12		 In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] CPSY2020-12 DC2020-12
pp.75-80
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
11:20		 Kanagawa Raiosha, Hiyoshi Campus, Keio University An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-74 CPSY2018-84 RECONF2018-48		 This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set ... [more] VLD2018-74 CPSY2018-84 RECONF2018-48
pp.13-18
VLD 2013-03-04
13:50		 Okinawa Okinawa Seinen Kaikan A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application
Junpei Kamei, Shingo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-136		 In error tolerant applications, some specific errors, which are of certain types or have severities within certain limit... [more] VLD2012-136
pp.1-6
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