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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SP | 2016-08-24 13:25 |
Kyoto | ACCMS, Kyoto Univ. | Daily Activity Recognition Based on Recurrent Neural Network Akira Tamamori, Tomoki Hayashi, Tomoki Toda, Kazuya Takeda (Nagoya Univ.)  SP2016-28 |
Our goal is to build an automatic surveillance system for elderly people and the core technique is daily activity recogn... [more] | SP2016-28 pp.7-12 |
| ICD | 2016-04-15 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C Satoru Nakanishi, Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Kurafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi (Renesas) ICD2016-15 |
A first-ever 90nm embedded 1T-MONOS Flash macro is presented to realize automotive reliability and simple process integr... [more] | ICD2016-15 pp.77-81 |
| MBE, NC (Joint) |
2016-03-22 11:00 |
Tokyo | Tamagawa University | An STDP control circuit and its evaluation using a Cu-MoOx-Al resistance change memory fabricated on a Si MOSFET Kazumasa Tomizaki, Takashi Morie, Hideyuki Ando (Kyushu Inst. Tech.), Atsushi Fukuchi, Masashi Arita, Yasuo Takahashi (Hokkaido Univ.) NC2015-70 |
With the progress of practical implementation of deep learning in neural networks, high-speed and low-power neural hardw... [more] | NC2015-70 pp.7-12 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 11:20 |
Kanagawa | Hiyoshi Campus, Keio University | An Architectural Optimization for Software Defined SSD using Full System Simulator Shun Gokita, Satoshi Kazama, Seiki Shibata, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa (FLL) VLD2015-103 CPSY2015-135 RECONF2015-85 |
In recent years, a kind of software-defined SSD which has a Flash control layer (FTL) in software teared out of hardware... [more] | VLD2015-103 CPSY2015-135 RECONF2015-85 pp.197-202 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses Kenta Shimazaki (Waseda Univ.), Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Yong-Jin Park, Nozomu Togawa (Waseda Univ.) VLD2015-75 DC2015-71 |
In conventional IP network, an IP router just forwards a packet to another router. Recently, Content Centric Networki... [more] |
VLD2015-75 DC2015-71 pp.243-248 |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-26 15:25 |
Miyagi | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.) VLD2015-30 ICD2015-43 IE2015-65 |
3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This pap... [more] | VLD2015-30 ICD2015-43 IE2015-65 pp.19-24 |
|
| RECONF | 2015-06-20 09:55 |
Kyoto | Kyoto University | A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) RECONF2015-15 |
Memory latency is the most serious design concern in computing centric architectures integrated with cache levels as a d... [more] | RECONF2015-15 pp.79-84 |
| VLD | 2015-03-03 16:15 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173 |
Non-volatile memory is superior to SRAM in terms of its high density and low leakage power but it consumes larger writ... [more] |
VLD2014-173 p.115 |
| CPSY | 2014-10-10 13:25 |
Chiba | Meeting Room 303, International Conference Hall, Makuhari-Messe | Theoretical Write Amplification Analysis of the SSD Shin-ichi Kanno, Hiroshi Yao (TOSHIBA), Daisuke Hashimoto (TAEC) CPSY2014-51 |
Theoretical limitation of write amplification and write speed of solid state drives (SSDs) are affected by page size and... [more] | CPSY2014-51 pp.25-30 |
| ICD | 2014-04-18 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | DataBase processor (DBP) which can search data ultra-high-speed
-- The Computing by Memory provides big innovation for information processing -- Katsumi Inoue (AOT), Cong-Kha Pham (UEC) ICD2014-18 |
Abstract The Processing burden of information search such as verification and recognition for conventional processor CPU... [more] | ICD2014-18 pp.91-96 |
| ICD, IPSJ-ARC | 2014-03-07 10:15 |
Aichi | Flexible Word-Parallel Euclidean Distance Search Associative Memory for Applications with Varying Dimensionality of Reference Vectors Toshinobu Akazawa, Hans Jurgen Mattausch (Hiroshima Univ.) ICD2013-138 |
The reported fully word-parallel associative memory architecture for nearest Euclidean distance (ED) search, which has f... [more] | ICD2013-138 pp.33-37 |
|
| NS, IN (Joint) |
2014-03-07 14:50 |
Miyazaki | Miyazaki Seagia | Optical and Electronic Combined Buffer Architecture for Optical Packet Switches Takahiro Hirayama, Takaya Miyazawa, Hiroaki Harai (NICT) NS2013-262 |
Optical packet switch (OPS) systems with fiber-delay-line (FDL) buffers provide high-throughput, energy-efficient, and t... [more] | NS2013-262 pp.497-502 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
STT-MRAM Architecture for Improving Throughput Haruki Mori, Koji Yanagida, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2013-110 |
STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory) attracts an attention as the substitute memory of SRAM. Th... [more] | ICD2013-110 p.27 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
Digital Word-Parallel Associative Memory for Smallest Euclidean Distance Search and Architecture verification in 180nm/65nm CMOS Toshinobu Akazawa, Hans Juergen Mattausch (Hiroshima Univ.) ICD2013-132 |
The reported digital word-parallel associative memory architecture for nearest Euclidean distance (ED) search is based o... [more] | ICD2013-132 p.77 |
| NS | 2013-10-17 15:20 |
Hokkaido | Hokkaido Univ. | A GPU Offloading method for improving performance of checksum computation in the TCP/IP stack Yuuki Tsubouchi, Go Hasegawa, Yoshiaki Taniguchi, Hirotaka Nakano, Morito Matsuoka (Osaka Univ.) NS2013-101 |
The size of ethernet frames is becoming larger and larger due to the utilization of Ethernet Jumbo Frame option, especi... [more] |
NS2013-101 pp.67-72 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 10:30 |
Aomori | A Memory Based Filed Programmable Device for Energy saving MCUs Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) VLD2013-46 ICD2013-70 IE2013-46 |
A Field Programmable Sequencer and memory (FPSM), which is an embedded memory based programmable peripherals for Micro C... [more] | VLD2013-46 ICD2013-70 IE2013-46 pp.1-6 |
|
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 16:30 |
Aomori | Set Operating Processor (SOP)
-- Application for Image recognition -- Katsumi Inoue (AOT), Duc-Hung Le, Masahiro Sowa, Cong-Kha Pham (UEC) VLD2013-53 ICD2013-77 IE2013-53 |
Abstract The Processing burden of information search such as verification and recognition for conventional processor CPU... [more] | VLD2013-53 ICD2013-77 IE2013-53 pp.35-40 |
|
| RECONF | 2013-09-19 14:15 |
Ishikawa | Japan Advanced Institute of Science and Technology | Development of Memory Management Framework for FPGA-based Prototyping Shinya Takamaeda-Yamazaki (Tokyo Inst. of Tech./JSPS Research Fellow), Kenji Kise (Tokyo Inst. of Tech.) RECONF2013-35 |
FPGA-based rapid prototyping supports faster emulation, but it requires the detailed implementation for each FPGA charac... [more] | RECONF2013-35 pp.91-96 |
| ICD | 2013-04-12 11:10 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
A High Performance Storage Class Memory/MLC NAND Hybrid SSD with Anti-Fragmentation Algorithm Kousuke Miyaji (Chuo Univ.), Hiroki Fujii (Univ. of Tokyo), Koh Johguchi (Chuo Univ.), Kazuhide Higuchi, Chao Sun (Univ. of Tokyo), Ken Takeuchi (Chuo Univ.) ICD2013-15 |
A 3D through-silicon-via (TSV) -integrated hybrid storage class memory (SCM)/multi-level-cell (MLC) NAND solid-state dri... [more] | ICD2013-15 pp.73-78 |
| VLD | 2013-03-05 15:35 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.) VLD2012-151 |
This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of... [more] |
VLD2012-151 p.89 |
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