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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS, IN (Joint) |
2024-03-01 14:50 |
Okinawa | Okinawa Convention Center | Real space sharing processing multihop networks Akira Tanaka (NIT, Tokyo College), Mitsuru Maruyama (KAIT), Shigeo Urushidani (NII), Toshiaki Tsujii (OMU)  NS2023-224 |
ICT is already widely prevalent. Along with it, processors, memories and other computational resources exist everywhere ... [more] | NS2023-224 pp.306-311 |
| SeMI | 2024-01-18 13:30 |
Yamanashi | Raki House Kaiji | Enhancing Human Skeleton Estimation with Multi-Frame mmWave Radar Point Cloud-based Method Xintong Shi, Tomoaki Ohtsuki (Keio Univ.) SeMI2023-52 |
Millimeter-Wave (mmWave) radar-based skeleton estimation has emerged as a focal point in the realm of human motion analy... [more] | SeMI2023-52 pp.18-21 |
| SANE | 2023-12-08 15:30 |
Overseas | Surakarta, Indonesia (Primary: On-site, Secondary: Online) |
Development of Reconfigurable NLFM Chirp Generator using FPGA Muhammad Hamka Ibrahim, Subuh Pramono (UNS), Josaphat Tetuko Sri Sumantyo (Chiba Univ) SANE2023-88 |
Nonlinear frequency modulation (NLFM) has advantages of suppressing the sidelobes. In this paper, the development of NLF... [more] | SANE2023-88 pp.153-155 |
| ICD | 2023-04-10 14:10 |
Kanagawa | (Primary: On-site, Secondary: Online) |
ICD2023-5 |
The information retrieval processors are processors that take over the information retrieval processing that current com... [more] | ICD2023-5 pp.10-13 |
| ICD | 2023-04-11 09:30 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
Development of A Variation-Tolerant Processing-In-Memory Architecture Using Discharging Current Calibration Daiki Kitagata, Shinji Tanaka, Naoya Fujita, Naoaki Irie (REL) ICD2023-8 |
Processing-in-memory (PIM) has recently been expected to be a key technology for endpoint intelligence since it can dram... [more] | ICD2023-8 p.16 |
| ICD | 2023-04-11 11:00 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Talk]
1 Tb 4b/Cell 176-Tier 3D NAND Flash with 4 Independent Planes for Read Tomoharu Tanaka (MMJ) ICD2023-9 |
In the presentation, a 1Tb 4b/cell 3D-NAND-Flash memory on a 176-tier technology with a 14.7Gb/mm2 bit density is shown ... [more] | ICD2023-9 p.17 |
| VLD, HWS [detail] | 2022-03-07 13:40 |
Online | Online | [Memorial Lecture]
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification Dehua Liang, Jun Shiomi, Noriyuki Miura (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.) VLD2021-84 HWS2021-61 |
Hyper-Dimensional (HD) computing is a brain-inspired learning approach for efficient and fast learning on today’s embedd... [more] | VLD2021-84 HWS2021-61 p.44 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS) VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 |
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] | VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 pp.19-24 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 14:40 |
Online | Online | Non Stop Processor with Non Volatile Element Shota Nakabeppu, Nao Sugiyama, Nobuyuki Yamasaki (Keio Univ.), Kenta Suzuki, Keizo Hiraga, Yasuo Kanda (Sony Semiconductor Solutions) CPSY2020-66 DC2020-96 |
In recent years, embedded systems such as wearable devices and robots have become widespread. Wear- able devices often ... [more] |
CPSY2020-66 DC2020-96 pp.97-102 |
| HWS, VLD [detail] | 2021-03-04 13:25 |
Online | Online | A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC) VLD2020-83 HWS2020-58 |
In this paper, we propose a highly efficient memory protection method based on the Tweakable block cipher (TBC). The lat... [more] | VLD2020-83 HWS2020-58 pp.85-90 |
| MBE, NC (Joint) |
2020-12-18 15:40 |
Online | Online | Time-delayed LSTM for historical time series Prediction Rin Adachi, Jun Rokui (Univ of Shizuoka) NC2020-30 |
The research which applies machine learning to the social time series prediction is actively carried out. Among them, ma... [more] | NC2020-30 pp.13-18 |
| RECONF | 2019-09-20 10:40 |
Fukuoka | KITAKYUSHU Convention Center | Multi-threaded High-Level Synthesis for Bandwidth-intensive Applications Jens Huthmann, Auter Podobas, Takaaki Miyajima, Atsushi Koshiba, Kentaro Sano (RIKEN) RECONF2019-30 |
Using stream computing on Field-Programmable Gate Arrays (FPGAs) has in the recent decades shown promise for practical ... [more] | RECONF2019-30 pp.51-56 |
| SCE | 2019-04-19 09:55 |
Tokyo | Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2019-2 |
SFQ/CMOS hybrid system, which is a hybridized system of SFQ circuits and CMOS memories, has been proposed as a large-sca... [more] | SCE2019-2 pp.7-11 |
|
| HWS, VLD | 2019-02-27 16:45 |
Okinawa | Okinawa Ken Seinen Kaikan | Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-105 HWS2018-68 |
FPGA-based manycore architectures attract an increasing attention in order to realize high-performance embedded systems.... [more] | VLD2018-105 HWS2018-68 pp.73-78 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima | Satellite Campus Hiroshima | A Case Study on Memory Architecture Exploration for FPGA-based Manycores Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-53 DC2018-39 |
In the design of high-performance embedded systems, FPGA-based manycores attract an increasing attention. In embedded sy... [more] | VLD2018-53 DC2018-39 pp.101-106 |
| ICD | 2018-04-20 09:55 |
Tokyo | [Invited Lecture]
A new core transistor equipped with NVM functionality without using any emerging memory materials Yasuhiro Taniguchi, Shoji Yoshida, Owada Fukuo, Yutaka Shinagawa, Hideo Kasai (Floadia), Lin Jia You, Wei I Huan (PTC), Daisuke Okada, Koichi Nagasawa, Kosuke Okuyama (Floadia) ICD2018-7 |
A tri-gate core transistor which has nonvolatile memory [NVM] functionality in midsection of a logic transistor gate was... [more] | ICD2018-7 pp.23-27 |
|
| MBE, NC (Joint) |
2018-03-13 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Statistical mechanics of coherent Ising machine
-- The case of infinite loading Hopfield model -- Toru Aonishi (Tokyo Tech.), Kazushi Mimura (Hiroshima City Univ.), Masato Okada (Univ. Tokyo), Yoshihisa Yamamoto (ImPACT/ Stanford Univ.) NC2017-69 |
The coherent Ising machine (CIM) has attracted attention as one of the most effective Ising computing architectures for ... [more] | NC2017-69 pp.9-14 |
| MBE, NC (Joint) |
2018-03-13 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Statistical mechanics of coherent Ising machine
-- The analysis of Hopfield model with discrete synapses -- Shunki Nakagawa, Toru Aonishi (Tokyo Tech.), Kazushi Mimura (Hiroshima City Univ.), Masato Okada (Univ. Tokyo), Yoshihisa Yamamoto (ImPACT/ Stanford Univ.) NC2017-70 |
The coherent Ising machine (CIM) is being developed as one of the Ising computing architecture for solving large-scale c... [more] | NC2017-70 pp.15-20 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A shared memory chip for twin-tower of chips Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Hideharu Amano (Keio Univ.) VLD2017-34 DC2017-40 |
A shared memory chip for the building-block computing system using ThruChip Interface (TCI) is developed and evaluated.T... [more] | VLD2017-34 DC2017-40 pp.43-48 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2017-03-10 17:00 |
Okinawa | Kumejima Island | A Scalable Data Centric Converged System for Big Data Analytics Yuki Sasaki, Kenji Takahashi, Keishi Sakanushi, Atsuhiro Kinoshita (Toshiba) CPSY2016-162 DC2016-108 |
Data analytics for IoT market is the most important issue today. Data needs to be converted to relevant information in a... [more] | CPSY2016-162 DC2016-108 pp.399-404 |
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