| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| R | 2015-10-16 11:00 |
Fukuoka | Irregularity Countermeasures in Massively Parallel BigData Processors Marat Zhanikeev (Kyutech)  R2015-53 |
The term Massively Parallel BigData Processor names a recent advance in bigdata processing technology which has advanced... [more] | R2015-53 pp.7-14 |
|
| DC, CPSY | 2011-04-12 13:25 |
Tokyo | A Note on Data Compression of Double-Precision Floating-Point Numbers for Massively Parallel Numerical Simulations Mamoru Ohara, Takashi Yamaguchi (TIRI) CPSY2011-2 DC2011-2 |
In numerical simulations using massively parallel computers like GPGPU (General-Purpose computing on Graphics Processing... [more] | CPSY2011-2 DC2011-2 pp.5-10 |
|
| SIS | 2008-06-13 12:50 |
Hokkaido | Application of the massively parallel embedded processor (MX) to real-time image processing Hiroyuki Yamasaki, Takeaki Sugimura, Hideyuki Noda, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) SIS2008-20 |
We developed the massively parallel embedded processor core (MX core) for the SoC(System on Chip) building in as an acce... [more] | SIS2008-20 pp.33-38 |
|
| ICD, ITE-CE | 2007-12-14 14:40 |
Kochi | A multi matrix-processor core architecture for real-time image processing SoC Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138 |
This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) archite... [more] | ICD2007-138 pp.107-111 |
|
| NC | 2007-11-18 12:30 |
Saga | Saga Univ. | Development of a Vision Chip with a Switched-Resistor Network Shosuke Morimoto, Seiji Kameda, Atsushi Iwata (Hiroshima Univ.) NC2007-55 |
A neuromorphic silicon retina carries out real-time image processing by massively-parallel circuit structure. A resi... [more] |
NC2007-55 pp.1-6 |
| CPSY | 2007-10-25 13:00 |
Kumamoto | Kumamoto University | The application of the massively parallel processor based on the matrix architecture Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24 |
We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] | CPSY2007-24 pp.1-5 |
| CPSY | 2007-10-25 13:40 |
Kumamoto | Kumamoto University | The program development method of the massively parallel processor based on the matrix architecture. Hiroyuki Yamasaki, Katsuya Mizumoto, Hideyuki Noda, Tetsu Nishijima, Kanako Yoshida, Takeaki Sugimura, Takashi Kurafuji, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-25 |
Recently, the installed applications in the digital devices has been remarkably progressed. Considering these background... [more] | CPSY2007-25 pp.7-12 |
| CPSY | 2007-10-25 14:20 |
Kumamoto | Kumamoto University | An Implementation and evaluation of Ant Colony Optimization for massively parallel SIMD processor MX Core Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) CPSY2007-26 |
We focus on massively parallel processor based on the matrix architecture (MX Core) developed by Renesas Technology Cor... [more] |
CPSY2007-26 pp.13-18 |
| SIP, ICD, IE, IPSJ-SLDM (Joint) [detail] |
2007-10-25 11:50 |
Fukushima | Aidu-Higasiyama-Onsen Kuturogijuku | An Analog Moving-Object-Localization VLSI System Employing OR-Amplification of Pixel Activities Yusuke Niki, Yasuo Manzawa, Satoshi Kametani, Tadashi Shibata (Univ. of Tokyo) SIP2007-114 ICD2007-103 IE2007-73 |
An analog VLSI for real-time moving object localization has been developed based on binarized pixel data (activity bits)... [more] | SIP2007-114 ICD2007-103 IE2007-73 pp.23-28 |
| ICD, IPSJ-ARC | 2006-06-09 14:00 |
Kanagawa | Design of a High Performance Vision Processor with Shared Memory Multi-SIMD Architecture Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa (The University of Tokyo) |
For high speed image recognition in real environment, it is a challenge to accelerate a large amount of calculation for ... [more] | ICD2006-56 pp.89-94 |
|
| ICD | 2006-05-25 13:00 |
Hyogo | Kobe University | A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture
-- A Very High Performance Processor IP for Mobile System-on-Chips -- Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) |
We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-b... [more] | ICD2006-25 pp.19-23 |
[Return to Top Page]