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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SCE | 2023-08-08 14:50 |
Kanagawa | Yokohama National Univ. (Primary: On-site, Secondary: Online) |
Majority-Logic-Based Approximate Adders Using Adiabatic Quantum-Flux-Parametron Mengmeng Wang (Yokohama National Univ.), Olivia Chen (Tokyo City Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.)  SCE2023-10 |
In this study, we propose several 2-bit approximate adders with different architectures, primarily utilizing five-input ... [more] | SCE2023-10 pp.49-52 |
| SCE | 2023-01-20 13:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
[Invited Talk]
A majority-booster gate and its application in adiabatic quantum-flux-parametron circuits Wataru Komiya, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2022-13 |
Adiabatic quantum-flux-parametron (AQFP) circuits express logic by means of a small current so that logic gates are requ... [more] | SCE2022-13 pp.1-5 |
| NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] | 2022-06-29 14:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
LSI implementation of analog CMOS majority circuit for neural network applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2022-27 IBISML2022-27 |
Majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. It can be applied to b... [more] | NC2022-27 IBISML2022-27 pp.189-192 |
| NLP, MICT, MBE, NC (Joint) [detail] |
2022-01-23 10:15 |
Online | Online | Analog CMOS implementation of majority logic for neuromorphic circuit applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2021-41 |
A majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. In addition to its c... [more] | NC2021-41 pp.45-48 |
| COMP | 2019-12-13 17:50 |
Gunma | Ikaho Seminar House, Gunma University | Depth Two Majority Circuits for Majority Yasuhiro Ojima, Takuya Yokokawa, Kazuyuki Amano (Gunma Univ.) COMP2019-44 |
Let $MAJ_n$ denote the Boolean majority function of $n$ input variables. In this paper, we study the construction of de... [more] |
COMP2019-44 pp.109-115 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Implementation and Optimization of Parallel Prefix Adder Using Majority Function Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2017-46 DC2017-52 |
In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration... [more] | VLD2017-46 DC2017-52 pp.109-114 |
| ICD | 2016-04-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi (Kobe Univ.), Koji Nii (Renesas Electronics), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2016-3 |
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology... [more] | ICD2016-3 pp.13-16 |
| SCE | 2016-01-21 10:45 |
Tokyo | Proposal of Majority Gate-Based Feedback Latches for AQFP Logic Naoki Tsuji, Naoki Takeuchi, Fumihiro China, Tatsuya Narama (Yokohama National Univ.), Thomas Ortlepp (CiS), Yamanashi Yuki, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2015-39 |
We have been developing the adiabatic quantum-flux-parametron (AQFP) as an ultra-low-power superconductor logic. Latches... [more] | SCE2015-39 pp.17-22 |
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| COMP | 2015-10-02 14:00 |
Tokyo | Some Aspects of Commutation in Clone Theory Hajime Machida COMP2015-26 |
Clone theory is motivated by logic (multiple-valued logic), algebra (universal algebra) and computer science (switching ... [more] | COMP2015-26 pp.23-28 |
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| COMP | 2006-06-23 11:10 |
Saitama | Saitama Univ. | Reductions for Monotone Boolean Circuits Kazuo Iwama, Hiroki Morizumi (Kyoto Univ.) |
The large class, say {\it NLOG}, of Boolean functions, including 0-1 Sort and 0-1 Merge, have an upper bound of $O(n\log... [more] | COMP2006-19 pp.15-19 |
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