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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2007-33 |
Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained types, its structure can ... [more] |
RECONF2007-33 pp.7-12 |
| MoNA, IN (Joint) |
2007-11-15 14:55 |
Fukuoka | Fukuoka Institute of Technology | NMF: Network Mining Framework using Topological Structure of Complex Networks Kouhei Sugiyama, Hiroyuki Ohsaki, Makoto Imase (Osaka Univ.), Takeshi Yagi, Junichi Murayama (NTT) IN2007-90 |
In this paper, we propose a network mining framework called NMF that supports integration of several link mining methods... [more] | IN2007-90 pp.7-12 |
| MoNA, IN (Joint) |
2007-11-16 14:00 |
Fukuoka | Fukuoka Institute of Technology | Packet transfer control forthe polling-based IPcommunications in micro-cellular network Tomoyuki Izumi, Takahiko Yamada (立命館大) IN2007-95 |
This paper discusses wireless interface control method for a unified micro-cellular network aimed at popularization of w... [more] | IN2007-95 pp.37-42 |
| RECONF | 2007-05-17 16:10 |
Ishikawa | Kanazawa Bunka Hall | Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits Yoshiaki Satou, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-7 |
Reconfigurable logic devices are classified into two type of logic block, which are coarse-grain and fine-grain by the b... [more] | RECONF2007-7 pp.37-42 |
| RECONF | 2007-05-17 17:20 |
Ishikawa | Kanazawa Bunka Hall | A Discussion on a Router for embedded Programmable Logic matriX (ePLX) Naoki Okuno, Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.), Takenobu Iwao, Hirofumi Nakano, Yoshihiro Okuno, Kazutami Arimoto (Renesas) RECONF2007-9 |
We propose a fine-grained programmable logic architecture designed to be embedded in system-on-chips (SoCs) to enhance t... [more] | RECONF2007-9 pp.49-54 |
| OPE, EMT, LQE, PN | 2007-01-30 13:50 |
Osaka | Osaka Univ. Convention Center | Adaptive laser processing system with a three-dimensional focus correction for the biological information-media Akihiro Takita, Yoshio Hayasaki (Univ. Tokushima) PN2006-73 OPE2006-155 LQE2006-144 |
The femtosecond laser processing system with target tracking feature was developed. The astigmatic focus error detection... [more] | PN2006-73 OPE2006-155 LQE2006-144 pp.147-150 |
| RECONF | 2005-11-30 15:05 |
Fukuoka | Kitakyushu International Conference Center | Implementation of Basic Function Blocks for Variable Grain Logic Cell Naoto Hamabe, Hideaki Nakayama, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
We can devide commercially avairable reconfigurable logic devices into two categories by processing data size, one is a ... [more] | RECONF2005-54 pp.7-12 |
| COMP | 2005-10-18 10:25 |
Miyagi | Tohoku Univ. | An asynchronous cellular space in which synchronous reversible cellular automata can be embedded Jin-Shan Qi, Kenichi Morita (Hiroshima Univ.) |
We proposed a 2-dimensional 2-state asynchronous cellular automaton in which asynchronous logic elements called a rotary... [more] | COMP2005-38 pp.15-20 |
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