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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, ICD | 2022-10-25 10:00 |
Shiga | (Primary: On-site, Secondary: Online) |
Hardware Evaluation of Romulus with Threshold Implementation and Its Simulation-Based Leakage Assessment Masaya Nemoto, Tamon Asano, Takeshi Sugawara (UEC)  HWS2022-30 ICD2022-22 |
This paper provides a third-party hardware performance evaluation of the NIST LWC finalist Romulus with threshold imple... [more] |
HWS2022-30 ICD2022-22 pp.1-5 |
| HCS | 2021-01-23 15:30 |
Online | Online | VR-based Verification Platform for Analyzing Panic Behavior in Indoor Disasters Jo Niino, Jun Ichikawa, Masanori Akiyoshi (Knagawa Univ.) HCS2020-56 |
Although many previous studies have investigated panic behavior in indoor disasters, there are some problems such as exp... [more] | HCS2020-56 pp.23-26 |
| IA, SITE, IPSJ-IOT [detail] | 2020-03-03 15:15 |
Online | Online | A Study of Currency-Basket-backed Stablecoins using Linear Logic Yusuke Kaneko (SMBC), Hitoshi Okada (NII), Shigeichiro Yamasaki (KINDAI Univ.) SITE2019-99 IA2019-77 |
Stablecoins circulating across international borders must be recorded without change in value of each of the constitue... [more] |
SITE2019-99 IA2019-77 pp.169-174 |
| QIT (2nd) |
2015-05-25 13:20 |
Osaka | Osaka University | [Poster Presentation]
Ground-state properties and dynamics of a generalized cluster model in one dimension Takumi Ohta (YITP, Kyoto Univ.), Shu Tanaka (Waseda Univ.), Ippei Danshita, Keisuke Totsuka (YITP, Kyoto Univ.) |
We study ground-state and dynamical properties in the one-dimensional cluster model with several interactions. First, we... [more] | |
| RECONF | 2014-06-12 10:50 |
Miyagi | Katahira Sakura Hall | An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6 |
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] | RECONF2014-6 pp.27-30 |
| ET | 2014-01-11 16:40 |
Tokyo | Mejiro University | A Teaching-materials Generation System Using A Logical Hierarchical Model of Information Moral Teaching-materials Tomohiro Enomoto, Yasuhiko Morimoto (Tokyo Gakugei Univ.), Shoichi Nakamura (Fukushima Univ.), Youzou Miyadera (Tokyo Gakugei Univ.) ET2013-88 |
Modifying many information morals teaching materials should be done by improving the technology in the information socie... [more] | ET2013-88 pp.121-126 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 10:35 |
Aomori | New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic Xu Bai, Michitaka Kameyama (Tohoku Univ.) VLD2013-57 ICD2013-81 IE2013-57 |
This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary d... [more] | VLD2013-57 ICD2013-81 IE2013-57 pp.59-64 |
|
| RECONF | 2012-09-18 15:15 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | An Area Minimized Logic Cluster using COGRE Logic Cell Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-32 |
These days, FPGAs (Field Programmable Gate Arrays) is required to increase in size and performance in order to deal w... [more] |
RECONF2012-32 pp.49-54 |
| MI | 2012-01-20 11:25 |
Okinawa | An Orientation Selective Filter Based Approach to Extract Sinusoids from HE-Stained Liver Specimens Masahiro Ishikawa, Sercan Taha Ahi, Fumikazu Kimura, Masahiro Yamaguchi, Hiroshi Nagahashi (Tokyo Tech), Akinori Hashiguchi, Michiie Sakamoto (Keio Univ.) MI2011-138 |
To analyze the structure of hepatic cords in HE-stained liver specimens, the extraction of sinusoids seems to be correct... [more] | MI2011-138 pp.337-342 |
|
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 11:15 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs Yuji Masumitsu, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2010-104 CPSY2010-59 RECONF2010-73 |
Feild programmable gate arrays (FPGAs) are mostly cluseter-based FPGAs. In a cluster-based FPGA, a logic block consists ... [more] | VLD2010-104 CPSY2010-59 RECONF2010-73 pp.139-144 |
| RECONF | 2010-05-13 15:20 |
Nagasaki | First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells Masahiro Koga, Masahiro Iida, Motoki Amagasaki (Kumamoto Univ.), Yoshinobu Ichida, Mitsuro Saji, Jun Iida (ROHM), Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-5 |
An advantage of a RLD such as an FPGA is that it can be customized after being manufactured. However, there is a problem... [more] | RECONF2010-5 pp.25-30 |
|
| VLD | 2010-03-11 10:00 |
Okinawa | Study of Via Programmable Logic Device VPEX for wiring architecture and Logic Array Block Shouta Yamada, Yuuichi Kokushou, Tomohiro Nishimoto, Naoyuki Yoshida, Ryohei Hori, Naoki Matsumoto, Tatsuya Kitamori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2009-107 |
We have developed the via-programmable logic device VPEX which was optimized for EB direct writing, and also developed t... [more] | VLD2009-107 pp.49-54 |
|
| SDM, ED | 2009-06-25 09:00 |
Overseas | Haeundae Grand Hotel, Busan, Korea | [Invited Talk]
Novel-Functional Single-Electron Devices Using Silicon Nanodot Array Yasuo Takahashi, Takuya Kaizawa, Mingyu Jo, Masashi Arita (Hokkaido Univ.), Akira Fujiwar, Yukinori Ono (NTT), Hiroshi Inokawa (Shizuoka Univ.), Jung-Bum Choi (Chungbuk National Univ.) ED2009-83 SDM2009-78 |
We demonstrate a highly functional Si nanodot array device that operates by means of single-electron effects. The device... [more] | ED2009-83 SDM2009-78 pp.145-148 |
| PRMU, IE, MI | 2009-05-28 10:30 |
Gifu | Gifu Univ. | Detection and Removal of Line Scratches Using Residual Information of Film Sequences with Spatial Filtering Yasuhiro Kazama, Masahide Abe, Masayuki Kawamata (Tohoku Univ.) IE2009-11 PRMU2009-2 MI2009-2 |
This paper proposes a method which detects and removes line scratches included in film sequences. First, we detect the s... [more] | IE2009-11 PRMU2009-2 MI2009-2 pp.5-10 |
| DC, CPSY | 2009-04-21 16:35 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Pulse Propagation Analysis for SER Evaluation of Logic Circuits Shoji Harada, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ) CPSY2009-9 DC2009-9 |
As a transistor feature size scales down in recent years, soft error tends to increase. In logic circuits, a pulse genar... [more] | CPSY2009-9 DC2009-9 pp.49-54 |
| PN | 2009-03-10 14:55 |
Okinawa | Yonaguni Island | Cycle Attack Free Logical Topology Design in OCDM Networks Yosuke Katsukawa, Shaowei Huang, Ken-ichi Kitayama (Osaka Univ.) PN2008-103 |
In OCDM networks there is a chance that cycle attack is caused by MAI(Multiaccess Interference) propagation and could di... [more] | PN2008-103 pp.111-116 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 15:10 |
Kanagawa | A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | VLD2008-121 CPSY2008-83 RECONF2008-85 pp.177-182 |
|
| HIP | 2008-11-07 - 2008-11-11 |
Ishikawa | Kanazawa Institute of Technology, Yamahiro Hot Spring | Analysis of relationship between physiological parameters and hand movements during playing Jenga Yasuhiro Takemura, Naoaki Itakura (The University of Electro-Communications) HIP2008-120 |
We focused on hand movements during playing Jenga and analyzed relationship between the finger tremor and the difference... [more] | HIP2008-120 pp.171-174 |
| RECONF | 2008-05-22 16:05 |
Fukushima | The University of Aizu | A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-8 pp.43-48 |
| SCE | 2008-01-25 15:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design and implementation of the SFQ half-precision floating point adder Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Koji Obata, Yuki Itou, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) |
A new project was started to develop a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SF... [more] | SCE2007-31 pp.35-40 |
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