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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2015-06-16 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Function Test of Latch-based Asynchronous Pipeline Circuits Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)  DC2015-19 |
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which ha... [more] | DC2015-19 pp.19-24 |
| VLD | 2015-03-03 09:15 |
Okinawa | Okinawa Seinen Kaikan | A low-power soft error tolerant latch scheme Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2014-162 |
In recent technology scaling, reduction of reliability by soft-error and increase power has appeared as an inevitable pr... [more] | VLD2014-162 pp.55-60 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 13:25 |
Miyagi | Local pulse generation in variable stages pipeline designs for low energy consumption Takayuki Nii, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Univ.), Masao Yanagisawa (Waseda Univ.) VLD2014-61 ICD2014-54 IE2014-40 |
The increase of energy consumption due to improved performance has become a problem in the mobile terminal, and various ... [more] | VLD2014-61 ICD2014-54 IE2014-40 pp.7-12 |
|
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 11:50 |
Aomori | A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) VLD2013-60 ICD2013-84 IE2013-60 |
In nano-scale manufacturing processes of integrated circuits, a impact of layout-dependent effects (LDEs) to circuit p... [more] |
VLD2013-60 ICD2013-84 IE2013-60 pp.77-82 |
|
| SANE | 2012-10-11 15:20 |
Overseas | The SONGDO CONVENSIA, Incheon Korea | Development of a hold release mechanism of a panel structure for Nano-Satellite Tatsuya Yoshino, Yuta Araki, Yasuyuki Miyazaki (Nihon Univ.) SANE2012-86 |
In recent years, Nano-Satellite which has various features is developed in each research institution. In this research, ... [more] | SANE2012-86 pp.169-172 |
| SDM, ED (Workshop) |
2012-06-27 18:45 |
Okinawa | Okinawa Seinen-kaikan | A Power-Efficient 4-PAM Serial Link Receiver using a fully differential Rail-to-Rail input Dynamic Latch for Wide Dynamic Range Junan Lee, Daeho Yun, Bongsub Song, Jinwook Burm (Sognag Univ.) |
This paper proposes a power-efficient 4-PAM serial link receiver using a fully differential rail-to-rail input dynamic l... [more] | |
| ISEC | 2011-12-14 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Uniquness Enhancement of PUF Responces Based on the Locations of Random Outputting RS Latches Dai Yamamoto (Fujitsu Lab.), Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta (Univ. of Electro-Comm.), Takao Ochiai, Masahiko Takenaka, Kouichi Itoh (Fujitsu Lab.) ISEC2011-68 |
Physical Unclonable Functions (PUFs) are expected to represent an important solution for secure ID generation and authen... [more] | ISEC2011-68 p.29 |
| DC, CPSY (Joint) |
2011-07-29 09:50 |
Kagoshima | Preliminary Experiment of A Clocking Scheme Enabling Dynamic Time Borrowing Shuji Yoshida, Satoshi Arima, Naruki Kurata (The Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Masahiro Goshima, Shuichi Sakai (The Univ. of Tokyo) CPSY2011-11 |
The feature size of LSI is getting smaller year by year, increasing random variability between the el- ements. These da... [more] |
CPSY2011-11 pp.13-18 |
|
| SCE | 2010-10-19 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Demonstration of SFQ readout operation for realizing SSPD array Hirotaka Terai, Shigehito Miki, Taro Yamashita, Kazumasa Makise, Zhen Wang (NICT) SCE2010-31 |
A readout circuit using superconducting single-flux-quantum (SFQ) circuits has been developed to realize an independentl... [more] | SCE2010-31 pp.43-48 |
| VLD | 2010-09-28 15:50 |
Kyoto | Kyoto Institute of Technology | Modeling of Latching Probability of Soft-Error-Induced Pulse Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) VLD2010-56 |
This paper describes soft error which is one of the dependability decrease factors of LSI(Large Scale Integrated circuit... [more] | VLD2010-56 pp.83-88 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 13:50 |
Kochi | Kochi City Culture-Plaza | [Invited Talk]
Failures due to Terrestriall Neutrons in Most Advanced Semicondutor Devices
-- Impacts and Hardening Techniques down to 22nm Design Rule -- Eishi Ibe, Kenichi Shimbo, Hitoshi Taniguchi, Tadanobu Toba (Hitachi, Ltd.) CPM2009-139 ICD2009-68 |
The status-of-the-art in failures and their mechanisms of CMOS memories and logic gates induced by terrestrial neutrons ... [more] | CPM2009-139 ICD2009-68 pp.29-34 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | Exploratory evaluation of a clocking scheme with relaxed timing constraint Takanobu Kita (Univ. of Tokyo), Shou Tarui (Hitachi Ltd.), Ryota Shioya (Univ. of Tokyo/Research Fellowship for Young Scientists DC), Masahiro Goshima, Shuichi Sakai (Univ. of Tokyo) CPSY2009-20 |
The feature size of LSI is getting smaller year by year, increasing random variation between the elements. These days, t... [more] | CPSY2009-20 pp.61-66 |
|
| SDM, ED | 2008-07-11 11:35 |
Hokkaido | Kaderu２・７ | A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Joon-Tae Jang, San-Hong Kim, Sung-Ki Kim, Taek-Soo Kim (Dongbu HiTek) ED2008-76 SDM2008-95 |
The holding voltage of the high-voltage devices the snapback breakdown condition has been known to be much smaller than ... [more] | ED2008-76 SDM2008-95 pp.193-197 |
| DC, CPSY | 2008-04-23 15:30 |
Tokyo | Tokyo Univ. | Influence of Untestable Hard Error on Soft Error Hardened Latches Kengo Nakashima, Kazuteru Namba, Hideo Ito (Chiba Univ) CPSY2008-8 DC2008-8 |
In recent high-density, high-speed and low-power VLSIs, soft errors frequently occur, and soft error hardened design bec... [more] | CPSY2008-8 DC2008-8 pp.43-48 |
| DC | 2008-02-08 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | ESD/Latch up Failure Analysis of CMOS LSI
-- Failure Mode Analysis with Atutual Data -- Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) DC2007-67 |
As the CMOS LSI advances, ESD/Latch-up problem is becoming more serious problem as a weakness of CMOS LSI structure. Thi... [more] | DC2007-67 pp.1-5 |
| CAS | 2008-02-01 09:00 |
Okinawa | Design Method of Latch design for absorption of clock skew Yuichi Nakamura (NEC) CAS2007-94 |
(To be available after the conference date) [more] | CAS2007-94 pp.1-6 |
|
| ED, SDM | 2007-06-25 14:40 |
Overseas | Commodore Hotel Gyeongju Chosun, Gyeongju, Korea | Design of HEMT Comparators for Ultrahigh-Speed A/D Conversion Hiroshi Watanabe,, Shunsuke Nakamura,, Takao Waho (Sophia Univ.) |
HEMT comparators for ultrahigh-speed A/D converters have been investigated. In particular, the transition times of the D... [more] | |
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