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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 37  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD 2024-01-29
17:00
Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis -- Toward comparative evaluation of latch-based and flip-flop-based circuits --
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-90 RECONF2023-93
As a synchronous logic circuit, it is often argued that latch-based circuits are superior to flip-flop circuits in terms... [more] VLD2023-90 RECONF2023-93
pp.59-64
RECONF, VLD 2024-01-29
17:25
Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)
Comparison of latch-based circuit and flip-flop-based circuit in actual device
Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-91 RECONF2023-94
The comparison results of current consumption, maximum operating frequency (Fmax) characteristics and minimum operating ... [more] VLD2023-91 RECONF2023-94
pp.65-70
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-17
15:40
Kumamoto Civic Auditorium Sears Home Yume Hall
(Primary: On-site, Secondary: Online)
VLD2023-79 ICD2023-87 DC2023-86 RECONF2023-82 Muller’s C-element is a basic component often used to rendezvous signals in asynchronous circuit designs. A lot of imple... [more] VLD2023-79 ICD2023-87 DC2023-86 RECONF2023-82
pp.255-260
DC 2023-02-28
16:15
Tokyo Kikai-Shinko-Kaikan Bldg
(Primary: On-site, Secondary: Online)
A Novel High Performance Scan-Test-Aware Hardened Latch with Improved Soft Error Tolerability
Ruijun Ma (AUST), Stefan Holst, Xiaoqing Wen (KIT), Hui Xu (AUST), Aibin Yan (AU) DC2022-91
The continuous pursuing of smaller technology nodes makes modern Integrated Circuits (ICs) more and more susceptible to ... [more] DC2022-91
pp.51-55
SDM, ICD, ITE-IST [detail] 2021-08-18
14:50
Online Online [Invited Talk] Latch Based Static and Dynamic Random Number Generators for Information Security
Hirofumi Shinohara, Kunyang Liu, Ruilin Zhang, Xingyu Wang (Waseda Univ.) SDM2021-42 ICD2021-13
This paper describes latch-based TRNG and PUF with highly stable operations [more] SDM2021-42 ICD2021-13
pp.64-67
DC 2021-02-05
11:35
Online Online A Novel High Performance Scan-Test-Aware Hardened Latch Design
Ruijun Ma, Stefan Holst, Xiaoqing Wen (KIT), Aibin Yan (AHU), Hui Xu (AUST) DC2020-71
As modern technology nodes become more and more susceptible to soft-errors, many radiation hardened latch designs have b... [more] DC2020-71
pp.12-17
SCE 2020-11-25
14:20
Online Online Design and bit-error-late evaluation of a Josephson latching driver using 10-kA/cm2 Nb process
Yuki Hironaka, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2020-8
We have been developing Josephson-CMOS hybrid memory, which is a combination of CMOS memory and Josephson logic circuits... [more] SCE2020-8
pp.1-6
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-17
10:55
Online Online DET Flip-Flops with SEU Detection Capability Using DICE and C-Element
Xu Haijia, Kazuteru Namba (Chiba Univ.) VLD2020-14 ICD2020-34 DC2020-34 RECONF2020-33
Abstract A dual-edge-triggered flip-flop (DET-FF) composed of DICE latch (Dual Interlocked Storage Cell) and C-element ... [more] VLD2020-14 ICD2020-34 DC2020-34 RECONF2020-33
pp.18-23
DC, CPSY, IPSJ-ARC [detail] 2020-10-12
14:10
Online Online Soft error tolerant SR latch using C-element
Ibuki Nakata, Kazuteru Namba (Chiba Univ) CPSY2020-19 DC2020-19
VLSI systems have become downsized, high integrated and low-power. As a result, the incidence of soft errors is increasi... [more] CPSY2020-19 DC2020-19
pp.12-15
DC 2020-02-26
16:35
Tokyo   Soft Error Tolerance of Power-Supply-Noise Hardened Latches
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2019-97
In recent years, with the scaling down and low-power operation of VLSI circuits, reliability degradation due to soft err... [more] DC2019-97
pp.67-72
SCE 2020-01-17
13:15
Kanagawa   [Poster Presentation] Optimization of a Josephson latching driver using 10-kA/cm2 Nb process for a Josephson-CMOS hybrid memory
Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2019-47
Josephson digital circuits such as single flux quantum circuits have a great potential for future high-end computing sys... [more] SCE2019-47
pp.73-74
SCE 2017-08-09
11:25
Aichi Nagoya Univ. (Higashiyama Campus) Energy evaluation of the feedback latch using AQFP logic
Mai Nozoe, Naoki Takeuti, Christopher Ayala, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2017-12
We are studying adiabatic quantum flux parametron (AQFP), which is an ultra-low-power superconductor device. We have bee... [more] SCE2017-12
pp.7-12
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:15
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations
Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43
According to the Moore's law, LSIs are miniaturized and the
reliability of LSIs is degraded. To improve the tolerance ... [more]
VLD2016-49 DC2016-43
pp.31-36
VLD, CAS, MSS, SIP 2016-06-17
15:50
Aomori Hirosaki Shiritsu Kanko-kan A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
A bit flip caused by voltage fluctuation, soft errors, and hardware Trojans becomes one of serious issues in the modern ... [more] CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33
pp.179-184
VLD 2016-02-29
16:15
Okinawa Okinawa Seinen Kaikan A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis
Keisuke Inoue (KTC), Mineo Kaneko (JAIST) VLD2015-117
This paper discusses a high-level synthesis of new latch-based architecture, HLS-gls.
The disadvantage of the conventio... [more]
VLD2015-117
pp.37-42
DC 2016-02-17
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) DC2015-96
According to the scaling down, and lower power design of VLSI circuits, power supply noise such as IR-drop affects the o... [more] DC2015-96
pp.61-66
SCE 2016-01-21
10:45
Tokyo   Proposal of Majority Gate-Based Feedback Latches for AQFP Logic
Naoki Tsuji, Naoki Takeuchi, Fumihiro China, Tatsuya Narama (Yokohama National Univ.), Thomas Ortlepp (CiS), Yamanashi Yuki, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2015-39
We have been developing the adiabatic quantum-flux-parametron (AQFP) as an ultra-low-power superconductor logic. Latches... [more] SCE2015-39
pp.17-22
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
15:55
Nagasaki Nagasaki Kinro Fukushi Kaikan A low-power soft error tolerant latch scheme on 15nm process
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2015-56 DC2015-52
In recent technology scaling, reliability of integrated circuits due to a soft error is becoming more critical than ever... [more] VLD2015-56 DC2015-52
pp.123-127
SCE 2015-08-04
15:45
Kanagawa Yokohama National Univ. Proposal and Demonstration of Magnetically Coupled Quantum Flux Latch
Naoki Tsuji, Naoki Takeuchi, Tatsuya Narama (Yokohama National Univ.), Thomas Ortlepp (CiS), Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2015-13
We have been developing the adiabatic quantum-flux-parametron (AQFP) as an ultra-low-power superconductor logic. In a pr... [more] SCE2015-13
pp.29-33
WIT, SP, ASJ-H, PRMU 2015-06-19
14:25
Niigata   A Prototype of a Braille Dot Controlling Mechanism by Using a Movable Top Panel and Latching
Li Yang, Tetsuya Watanabe (Niigata Univ.) PRMU2015-58 SP2015-27 WIT2015-27
To develop a multi-line refreshable braille display, we devised a dot controlling mechanism by using a movable top panel... [more] PRMU2015-58 SP2015-27 WIT2015-27
pp.153-156
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