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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2017-03-02 15:50 |
Okinawa | Okinawa Seinen Kaikan | MILP Approach to Skew-Aware High Level Synthesis Kai Shimura, Mineo Kaneko (JAIST)  VLD2016-120 |
Intentional clock skew is known as one of the promising techniques for enhancing the circuit speed. However, when we tr... [more] |
VLD2016-120 pp.97-102 |
| VLD | 2017-03-03 13:25 |
Okinawa | Okinawa Seinen Kaikan | Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2016-129 |
Due to the downsizing of VLSI, reliability issues caused by soft-errors have become more explicit. Several studies in sy... [more] | VLD2016-129 pp.151-156 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:15 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design for 3-Demensional Sound Processor using a High-Level Synthesis Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) RECONF2016-40 |
High quality sound systems are penetrated into our lifestyle in various fields. In recent years, Minimized audio spot ge... [more] | RECONF2016-40 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2016-69 DC2016-63 |
We propose data transfer optimization in accelerator design with high-level synthesis. Typical accelerator designs perfo... [more] | VLD2016-69 DC2016-63 pp.147-152 |
| NS | 2016-10-20 13:50 |
Hyogo | Himeji Nishi-Harima Area Jibasan Center | Distributed Packet Processing Architecture using Hardware Accelerators for 100Gbps Forwarding Throughput on Virtualized Edge Router Satoshi Nishiyama, Hitoshi Kaneko, Ichiro Kudo (NTT) NS2016-90 |
To implement virtualized service edge functions on carrier networks by general-purpose servers, it is necessary to impro... [more] | NS2016-90 pp.13-18 |
| DC | 2016-06-20 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14 |
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] | DC2016-14 pp.25-30 |
| VLD, IPSJ-SLDM | 2016-05-11 14:30 |
Fukuoka | Kitakyushu International Conference Center | A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] | VLD2016-4 pp.41-46 |
| VLD, IPSJ-SLDM | 2016-05-11 14:55 |
Fukuoka | Kitakyushu International Conference Center | A Note on Scheduling Problem Considering the Radiation Resistance of Registers Keisuke Inoue (KTC), Mineo Kaneko (JAIST) |
This paper discusses a high-level design of an application specific integrated circuit (ASIC) with radiation resistance.... [more] | |
| VLD | 2016-02-29 15:00 |
Okinawa | Okinawa Seinen Kaikan | High-Level Synthesis of Embedded Systems Controller from Erlang Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2015-114 |
This article presents a method of specifying the behavior of embedded systems' control by a subset of Erlang and synthes... [more] | VLD2015-114 pp.19-24 |
| VLD | 2016-02-29 15:50 |
Okinawa | Okinawa Seinen Kaikan | ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components Junghoon Oh, Mineo Kaneko (JAIST) VLD2015-116 |
As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VL... [more] | VLD2015-116 pp.31-36 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 13:25 |
Kanagawa | Hiyoshi Campus, Keio University | A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87 |
Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] | VLD2015-105 CPSY2015-137 RECONF2015-87 pp.209-214 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2015-60 DC2015-56 |
This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchr... [more] | VLD2015-60 DC2015-56 pp.147-152 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2015-61 DC2015-57 |
This paper proposes an extension of distributed control, which enables efficient run-time scheduling of variable latency... [more] | VLD2015-61 DC2015-57 pp.153-158 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components Junghoon Oh, Mineo Kaneko (JAIST) VLD2015-62 DC2015-58 |
As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VL... [more] | VLD2015-62 DC2015-58 pp.159-164 |
| VLD | 2015-03-03 10:20 |
Okinawa | Okinawa Seinen Kaikan | ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2014-164 |
As the device size decreases, reliability degradation caused by soft-errors has become one of the greatest issues in VLS... [more] | VLD2014-164 pp.67-72 |
| VLD | 2015-03-03 11:35 |
Okinawa | Okinawa Seinen Kaikan | A Virtual/Real Combined Verification Method for FPGAs Yoshimasa Ishino (MMS) VLD2014-167 |
The biggest advantage of FPGA is that can change the circuits at any time. Therefore, verification in virtual stage beco... [more] | VLD2014-167 pp.85-89 |
| DC | 2015-02-13 14:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Method of Scheduling in High-Level Synthesis for Hierarchical Testability Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-84 |
We previously proposed a binding method for hierarchical testability to increase the number of hierarchically testable f... [more] | DC2014-84 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] | VLD2014-85 DC2014-39 pp.99-104 |
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