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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS (Joint) |
2018-02-28 16:55 |
Okinawa | Okinawa Seinen Kaikan | Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST)  VLD2017-102 |
Among several problems with miniaturization of LSIs, soft-errors are one of serious problems to make reliability worse. ... [more] | VLD2017-102 pp.79-84 |
| VLD, HWS (Joint) |
2018-03-01 16:00 |
Okinawa | Okinawa Seinen Kaikan | A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit Takuya Okamoto, Ryota Yamamoto, Shinya Honda (Nagoya Univ.) VLD2017-116 |
Today, Deep Neural Network (DNN) is utilized in various fields. There is a demand for deep learning in the field of embedd... [more] | VLD2017-116 pp.163-168 |
| VLD, HWS (Joint) |
2018-03-01 16:25 |
Okinawa | Okinawa Seinen Kaikan | A Concept of DNN Framework for Embedded System Using FPGA Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC) VLD2017-117 |
Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system. For an em... [more] |
VLD2017-117 pp.169-174 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 17:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2017-75 CPSY2017-119 RECONF2017-63 |
This paper presents a distributed memory architecture for dedicated hardware automatically synthesized from Erlang prog... [more] |
VLD2017-75 CPSY2017-119 RECONF2017-63 pp.77-82 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 14:50 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | VLD2017-85 CPSY2017-129 RECONF2017-73 |
(To be available after the conference date) [more] | VLD2017-85 CPSY2017-129 RECONF2017-73 pp.145-150 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) VLD2017-28 DC2017-34 |
A three-dimensional (3D) sound processor architecture that includes 3D sound processing intellectual property (IP) cores... [more] | VLD2017-28 DC2017-34 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 10:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table Yuji Shindo, Kenshu Seto, Hao San (TCU) VLD2017-44 DC2017-50 |
We propose an area reduction method of digital circuit part in analog-to-digital converter (ADC) based on β-expansion. T... [more] | VLD2017-44 DC2017-50 pp.101-104 |
| RECONF | 2017-09-26 13:55 |
Tokyo | DWANGO Co., Ltd. | A case study of High-level Synthesis Using Higher-order Function on Functional Language Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35 |
The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forc... [more] | RECONF2017-35 pp.75-80 |
| VLD, IPSJ-SLDM | 2017-05-10 13:30 |
Fukuoka | Kitakyushu International Conference Center | VLD2017-1 |
In this paper, we present techniques to automatically generate high-level C description after ECO (Engineering Change Or... [more] | VLD2017-1 pp.1-6 |
| VLD | 2017-03-01 15:55 |
Okinawa | Okinawa Seinen Kaikan | A Design Technique for Approximate Circuits based on Artificial Neural Network Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-106 |
This paper proposes a design technique for approximate circuits based on artificial neural network, and then evaluates t... [more] | VLD2016-106 pp.25-30 |
| VLD | 2017-03-01 16:20 |
Okinawa | Okinawa Seinen Kaikan | Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models Shogo Senba, Hiroshi Saito (UoA) VLD2016-107 |
This paper proposes a transformation tool that generates an asynchronous Register Transfer Level (RTL) model with bundle... [more] | VLD2016-107 pp.31-36 |
| VLD | 2017-03-02 15:00 |
Okinawa | Okinawa Seinen Kaikan | Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis Xiaoguang Li, Mineo Kaneko (JAIST) VLD2016-118 |
The performance of data path circuit can be improved by shifting the clock signal arrival time intentionally. In order t... [more] | VLD2016-118 pp.85-90 |
| VLD | 2017-03-02 15:50 |
Okinawa | Okinawa Seinen Kaikan | MILP Approach to Skew-Aware High Level Synthesis Kai Shimura, Mineo Kaneko (JAIST) VLD2016-120 |
Intentional clock skew is known as one of the promising techniques for enhancing the circuit speed. However, when we tr... [more] |
VLD2016-120 pp.97-102 |
| VLD | 2017-03-03 13:25 |
Okinawa | Okinawa Seinen Kaikan | Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2016-129 |
Due to the downsizing of VLSI, reliability issues caused by soft-errors have become more explicit. Several studies in sy... [more] | VLD2016-129 pp.151-156 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:15 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design for 3-Demensional Sound Processor using a High-Level Synthesis Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) RECONF2016-40 |
High quality sound systems are penetrated into our lifestyle in various fields. In recent years, Minimized audio spot ge... [more] | RECONF2016-40 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Hardware implementation of PLC Instructions by high level synthesis Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT) RECONF2016-43 |
The hardware implementation of instruction sequence is a method to conceal and to protect the intellectual property. ... [more] |
RECONF2016-43 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2016-69 DC2016-63 |
We propose data transfer optimization in accelerator design with high-level synthesis. Typical accelerator designs perfo... [more] | VLD2016-69 DC2016-63 pp.147-152 |
| NS | 2016-10-20 13:50 |
Hyogo | Himeji Nishi-Harima Area Jibasan Center | Distributed Packet Processing Architecture using Hardware Accelerators for 100Gbps Forwarding Throughput on Virtualized Edge Router Satoshi Nishiyama, Hitoshi Kaneko, Ichiro Kudo (NTT) NS2016-90 |
To implement virtualized service edge functions on carrier networks by general-purpose servers, it is necessary to impro... [more] | NS2016-90 pp.13-18 |
| DC | 2016-06-20 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14 |
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] | DC2016-14 pp.25-30 |
| RECONF | 2016-05-20 09:00 |
Kanagawa | FUJITSU LAB. | [Invited Talk]
Altera OpenCL SDK with Spectra-Q, the latest technology trend and the applications Spectra-Q: The latest technology and applications, including OpenCL SDK Yukitaka Takemura (Altera JP) RECONF2016-17 |
Recently the resources of FPGA have been increasing dramatically, and therefore a big improvement of the design tools co... [more] | RECONF2016-17 p.83 |
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