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Committee Date Time Place Paper Title / Authors Abstract Paper #
ISEC, SITE, LOIS 2019-11-02
10:00		 Osaka Osaka Univ. Evolving Secret Sharing: Hierarchical Access Structure with Polynomial Share Size
Sabyasachi Dutta (Univ. of Calgary), Partha Sarathi Roy, Kazuhide Fukushima, Shinsaku Kiyomoto (KDDI Research), Kouichi Sakurai (Kyushu Univ.) ISEC2019-76 SITE2019-70 LOIS2019-35		 Secret sharing allows storing secret information in a distributed manner among several participants.
The original setti... [more]		 ISEC2019-76 SITE2019-70 LOIS2019-35
pp.93-98
WBS, IT, ISEC 2018-03-08
09:25		 Tokyo Katsusika Campas, Tokyo University of Science A study on hierarchical secret sharing schemes applicable to any level based on XOR operations
Koji Shima, Hiroshi Doi (IISEC) IT2017-118 ISEC2017-106 WBS2017-99		 Hierarchical secret sharing schemes are known for how they share a secret among a group of participants partitioned into... [more] IT2017-118 ISEC2017-106 WBS2017-99
pp.81-88
NS, RCS
(Joint)		 2011-12-16
14:40		 Yamaguchi Yamaguchi University Duplicate Address Detection Method for MANET Using Hierarchical Network Infra-Structure
Yuta Matsuno, Shigetomo Kimura, Yoshihiko Ebihara (Univ of Tsukuba) NS2011-142		 The authors have proposed a method to construct network infrastructure connecting ARs (Access Routers) and their uplink ... [more] NS2011-142
pp.137-142
IBISML 2010-11-05
15:30		 Tokyo IIS, Univ. of Tokyo [Poster Presentation] Statistical mechanical analysis of hierarchical random code ensemble in signal processing
Koujin Takeda (Tokyo Tech.), Tomoyuki Obuchi (Osaka Univ.), Kazutaka Takahashi (Tokyo Tech.) IBISML2010-90		 The relation between signal processing in information science and statistical physics has been intensively discussed. In... [more] IBISML2010-90
pp.231-238
ICD 2010-04-22
15:45		 Kanagawa Shonan Institute of Tech. A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout
Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10		 A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] ICD2010-10
pp.53-57
ISEC 2007-09-07
09:50		 Tokyo Kikai-Shinko-Kaikan Bldg. A Study on Hierarchical Secret Sharing Schemes Using Product and Concatenated Codes
Chigusa Kawashima (Polytechnic Univ.), Takahiro Yoshida (Waseda Univ.), Tomoko K. Matsushima (Polytechnic Univ.) ISEC2007-76		 In this paper, two secret sharing schemes with a hierarchical access structure are investigated. One scheme is based on ... [more] ISEC2007-76
pp.17-23
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