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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2019-02-27 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan | Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework Masataka Aoki, Yukihide Kohira (Univ. of Aizu)  VLD2018-102 HWS2018-65 |
In general-synchronous framework (g-frame), in which a clock is not assumed to be distributed to all registers simultane... [more] | VLD2018-102 HWS2018-65 pp.55-60 |
| VLD, HWS (Joint) |
2018-03-01 13:00 |
Okinawa | Okinawa Seinen Kaikan | An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit Yuki Arai, Shuji Tsukiyama (Chuo Univ.) VLD2017-110 |
In general-synchronous framework, the clock signal is distributed to each register in optimal individual timing, so that... [more] | VLD2017-110 pp.127-132 |
| SIP, CAS, MSS, VLD | 2017-06-20 15:30 |
Niigata | Niigata University, Ikarashi Campus | Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit Yuta Ukon, Shimpei Sato, Atsushi Takahashi (Tokyo Inst. of Tech.) CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23 |
There are a lot of high load processing that is not required high accuracy at the data center. An approximate computing ... [more] | CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23 pp.119-124 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 09:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH) VLD2016-95 CPSY2016-131 RECONF2016-76 |
When variable latency for digital circuits are assumed, circuits can work with a small clock period that has the possib... [more] |
VLD2016-95 CPSY2016-131 RECONF2016-76 pp.165-170 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 13:35 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA Manri Terada, Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-48 DC2016-42 |
Recently, the logic circuits are implemented to FPGA in many fields. To achieve faster circuits, a design flow to imple... [more] |
VLD2016-48 DC2016-42 pp.25-30 |
| VLD | 2016-03-02 11:20 |
Okinawa | Okinawa Seinen Kaikan | Performance Improvement by Engineering Change Order in General-Synchronous Framework for Altera FPGA Hayato Mashiko, Takuya Oba, Yukihide Kohira (Univ. of Aizu) VLD2015-137 |
Recently, the logic circuits are implemented to FPGA instead of ASIC in many fields. However, the circuit implemented to... [more] | VLD2015-137 pp.149-154 |
| VLD | 2016-03-02 13:50 |
Okinawa | Okinawa Seinen Kaikan | Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Tech) VLD2015-140 |
General synchronous circuits are proposed as having taken the place of complete synchronous circuits and do not necessar... [more] | VLD2015-140 pp.167-172 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 11:10 |
Oita | B-ConPlaza | Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu) VLD2014-83 DC2014-37 |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] | VLD2014-83 DC2014-37 pp.87-92 |
| VLD | 2014-03-05 16:10 |
Okinawa | Okinawa Seinen Kaikan | Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling Tatsuya Masui, Yukihide Kohira (Univ. of Aizu) VLD2013-167 |
Recently, instead of implementation into ASIC, implementation into FPGA is used in many fields. However, in general, cir... [more] | VLD2013-167 pp.183-188 |
| VLD | 2010-03-11 16:55 |
Okinawa | Clustering Method for Low Power Clock Tree in General Syncrhonous Framework Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Osaka univ) VLD2009-119 |
In general synchronous framework, in which the clock is not assumed to be distributed to all registers simultaneously, t... [more] | VLD2009-119 pp.121-126 |
|
| VLD | 2009-03-11 15:50 |
Okinawa | A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-134 |
Clock trees for general synchronous framework can be synthesized by using a clock tree synthesis (CTS) engine in EDA sys... [more] | VLD2008-134 pp.47-52 |
|
| VLD | 2009-03-11 16:15 |
Okinawa | A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-135 |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] | VLD2008-135 pp.53-58 |
|
| CAS | 2008-02-01 10:55 |
Okinawa | A Fast Modification Algorithm for Shortest Path Tree and its Performance Evaluation Tsutomu Ishida, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) CAS2007-98 |
In VLSI design, circuits are improved by circuit modifications.The minimum feasible clock period of a circuit is one of ... [more] | CAS2007-98 pp.25-30 |
|
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 13:10 |
Miyagi | [Invited Talk]
General synchronous circuits using global clock
-- design methodologies, tools, and prospects -- Atsushi Takahashi (Tokyo Inst. of Tech.) |
In current VLSI design, most digital circuits are synthesized as synchronous circuits which are synchronized by global c... [more] | SIP2006-110 ICD2006-136 IE2006-88 pp.55-60 |
|
| SDM, VLD | 2006-09-25 13:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Peak Power Reduction in LSI by Clock Scheduling Yosuke Takahashi, Atsushi Takahashi (Tokyo Tech) |
The reduction of peak power consumption of LSI is required to reduce the instability of gate operation, the delay increa... [more] | VLD2006-35 SDM2006-156 pp.7-12 |
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