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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2015-03-04 13:25 |
Okinawa | Okinawa Seinen Kaikan | A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2014-182 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2014-182 pp.165-170 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 10:50 |
Kanagawa | Hiyoshi Campus, Keio University | A Hardware Trojan Detection Method based on Trojan net features Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-137 CPSY2014-146 RECONF2014-70 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2014-137 CPSY2014-146 RECONF2014-70 pp.157-162 |
| MW, ED | 2015-01-16 09:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 10 MHz to 12 GHz Low-Distortion High-Speed SP4T Switch for RF ATE Using TaON Passivation GaN HEMTs Masayuki Kimishima, Satosi Koyama, Masao Onishi (Advantest Lab,) ED2014-125 MW2014-189 |
A 10 MHz – 12 GHz low distortion high speed single pole 4 throw (SP4T) GaN HEMT switch for RF Automated Test Equip... [more] | ED2014-125 MW2014-189 pp.47-51 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:30 |
Oita | B-ConPlaza | A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45 |
Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry. This circumstan... [more] |
VLD2014-91 DC2014-45 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | Optimization for gate-level pipelined self-synchrnous circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-107 DC2014-61 pp.233-238 |
| SP, ASJ-H | 2014-10-23 14:00 |
Wakayama | Nanki Shirahama Onsen Hotel Seamore | Interaural difference to produce spatially segregated sound from two white noises Daisuke Morikawa (JAIST) |
This paper clarifies the role of interaural time difference (ITD) and interaural level difference (ILD) in localization ... [more] | SP2014-83 pp.43-48 |
| SDM | 2013-12-13 09:20 |
Nara | NAIST | Electrical characteristics of ALD-Al2O3 gate dielectric on n-GaN treated by high pressure water vapor annealing Koji Yoshitsugu, Tomoaki Umehara, Masahiro Horita, Yasuaki Ishikawa, Yukiharu Uraoka (NAIST) SDM2013-117 |
In this paper, we investigated the effect of high pressure water vapor annealing (HPWVA) as a post deposition annealing ... [more] | SDM2013-117 pp.7-11 |
| SANE | 2013-07-26 13:00 |
Tokyo | Electric Navigation Research Institute | A study on departure queue reduction based on predicted runway usage Midori Sumiya, Hisae Aoyama, Izumi Yamada, Mark Brown (ENRI) SANE2013-37 |
In response to increasing air traffic levels, it has become necessary to take steps to improve the efficiency of airport... [more] | SANE2013-37 pp.1-6 |
| SDM | 2011-07-04 13:20 |
Aichi | VBL, Nagoya Univ. | Effect of O2 Annealing for Al2O3/Ge Structure on Interfacial Properties Shigehisa Shibayama, Kimihiko Kato, Mitsuo Sakashita, Wakana Takeuchi, Osamu Nakatsuka, Shigeaki Zaima (Nagoya Univ.) SDM2011-59 |
For realizing the next generation complementary metal-oxide-semiconductor field-effect-transistors (CMOSFETs), High-k/Ge... [more] | SDM2011-59 pp.51-56 |
| VLD | 2011-03-04 13:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | An evaluation of error detection/correction circuits by gate level simulation Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141 |
In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period su... [more] | VLD2010-141 pp.147-152 |
| EMD, R | 2011-02-18 15:25 |
Shizuoka | Shizuoka Univ. (Hamamatsu) | Logic stabilization of unstable logic circuit with open fault Taiki Yasutomi, Masaru Sanada (KUT) R2010-47 EMD2010-148 |
An experiment for stabilization of output logic brought by floating gate fault with unsuitable electric value has been e... [more] | R2010-47 EMD2010-148 pp.31-36 |
| SDM | 2010-11-11 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Comprehensive understanding of oxygen vacancy induced effective work function modulation in high-k/metal gate stacks Takuji Hosoi, Masayuki Saeki, Yuki Kita, Yudai Oku, Hiroaki Arimura, Naomu Kitano (Osaka Univ.), Kenji Shiraishi, Keisaku Yamada (Univ. Tsukuba), Takayoshi Shimura, Heiji Watanabe (Osaka Univ.) SDM2010-175 |
Effective work function of p-type gate electrodes on Hf-based high-k dielectrics is known to decrease after high tempera... [more] | SDM2010-175 pp.23-28 |
| ED, SDM | 2010-07-02 12:00 |
Tokyo | Tokyo Inst. of Tech. Ookayama Campus | The Analysis of Temperature Dependency of the Mobility In High-k/Metal Gate MOSFET and the Performance on its CMOS Inverter Takeshi Sasaki, Takuya Imamoto, Tetsuo Endoh (Tohoku Univ.) ED2010-92 SDM2010-93 |
As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials h... [more] | ED2010-92 SDM2010-93 pp.177-182 |
| ED | 2010-06-18 11:50 |
Ishikawa | JAIST | Photo corrosion of Metal Gate Electrodes during Wet Daisuke Watanabe (Daikin Industries,Ltd.), Chiharu Kimura, Hidemitsu Aoki (Osaka Univ.) ED2010-46 |
Wet processes for removing high-k film involve the risk of enhanced galvanic corrosion at the gate electrode level. We f... [more] | ED2010-46 pp.69-74 |
| EE | 2010-01-22 10:15 |
Fukuoka | Simulation of Power Dissipation at MOSFET Gate Port of Class E Amplifier Shouichirou Yonekura, Taishi Matsuzaki, Tadashi Suetsugu (Fukuoka Univ.) EE2009-42 |
In this paper, gate port power dissipation of class E amplifier is obtained as a function of amplitude and offset of dri... [more] | EE2009-42 pp.37-40 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 14:05 |
Kochi | Kochi City Culture-Plaza | Logic stabilization way of open fault with unsuitable logic
-- Aim in simple diagnosis technology -- Masaru Sanada (Koch Univ. of Tech.), Keishi Hashida (Renesas Design), Taiki Yasutomi (Koch Univ. of Tech.) VLD2009-64 DC2009-51 |
An experiment for stabilization of output logic brought by floating gate fault with unsuitable electric value has been e... [more] | VLD2009-64 DC2009-51 pp.161-166 |
| NC, MBE (Joint) |
2009-11-13 10:25 |
Miyagi | Tohoku Univ. | Somatosensory evoked potentials during NREM and REM sleep Hiroyuki Inada, Akihiro Karashima, Norihiro Katayama, Mitsuyuki Nakao (Tohoku Univ.) MBE2009-63 |
There is a hypothesis that the thalamus is the primary structure involved in closing the sensory gate during sleep. Rece... [more] | MBE2009-63 pp.7-12 |
| ED | 2009-04-23 15:30 |
Miyagi | Tohoku Univ. | Ferroelectric-Gate Thin-Film-Transistor Memory Using Epitaxially Grown Composite-Oxide-Film Yukihiro Kaneko, Hiroyuki Tanaka, Yoshihisa Kato, Yasuhiro Shimada (Panasonic Corp.) ED2009-5 |
We have developed a ferroelectric-gate thin-film transistor (FeTFT) composed of heteroepitaxially stacked oxide material... [more] | ED2009-5 pp.17-22 |
| SDM, ED | 2008-07-10 10:15 |
Hokkaido | Kaderu２・７ | Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering(GIBL) Seongjae Cho, Il Han Park, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park (Seoul National Univ.) ED2008-58 SDM2008-77 |
Recently, various 3-D nonvolatile memory (NVM) devices have been researched for improving the degree of integration. NVM... [more] | ED2008-58 SDM2008-77 pp.95-99 |
| VLD, CAS, SIP | 2008-06-27 09:40 |
Hokkaido | Hokkaido Univ. | An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (NAIST) CAS2008-21 VLD2008-34 SIP2008-55 |
Information on false paths in a circuit is useful for design and test. The use of this information may contribute not o... [more] | CAS2008-21 VLD2008-34 SIP2008-55 pp.13-18 |
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