| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2007-05-18 10:00 |
Ishikawa | Kanazawa Bunka Hall | MuCCRA-D:A Dynamically Reconfigurable Processor with Directly Interconnected PEs Masaru Kato, Yohei Hasegawa, Hideharu Amano (Keio Univ.)  RECONF2007-12 |
MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, uses a typical i... [more] |
RECONF2007-12 pp.67-72 |
| VLD, IPSJ-SLDM | 2007-05-10 14:55 |
Kyoto | Kyodai Kaikan | A Modeling of Dynamically Reconfigurable Processor using SystemC Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu) |
Recently, dynamically reconfigurable processors (DRPs) based on FPGA technology are proposed. DRPs are implemented on... [more] |
VLD2007-4 pp.19-24 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 16:35 |
Fukuoka | Kitakyushu International Conference Center | A Self-Test of Dynamically Reconfigurable Processors Takashi Fujii, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
Dynamically Reconfigurable Processor (DRP), which can execute a task with multiple hardware contexts so as to achieve hi... [more] | VLD2006-62 DC2006-49 pp.65-70 |
| SDM, VLD | 2006-09-26 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) |
This paper proposes a novel processor for genetic algorithm (GA) using dynamically reconfigurable memory. Ingeneral GA, ... [more] | VLD2006-39 SDM2006-160 pp.1-6 |
| CPSY, DC | 2006-04-14 10:40 |
Tokyo | Takeda Hall | Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices Kentaroh Katoh, Yumin Yao, Kazuteru Namba, Hideo Ito (チバダイ) |
This paper proposes a BIST (Built-In Self Test) method for testing the PEs (Processing Elements) of multi-context based ... [more] | CPSY2006-4 DC2006-4 pp.19-24 |
| ICD, VLD | 2006-03-10 13:35 |
Okinawa | A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Technology Teruhito Tanaka, Kouji Hatada, Tetsuya Konishi, Yoshikazu Odajima, Takashi Kambe (Kinki Univ.) |
Reed-Solomon Decoder can correct continued errors and it has been a popular technology for various devices such as commu... [more] | VLD2005-128 ICD2005-245 pp.37-42 |
|
| RECONF | 2005-11-30 16:10 |
Fukuoka | Kitakyushu International Conference Center | Implementation of 1-D/2-D FFT on the Dynamically Reconfigurable Processor DAPDNA-2 Kosuke Shiba, Atsushi Imaizumi, Takeshi Sakuma (IPFlex) |
The Fast Fourier Transform (FFT), which is applied to extensive fields as a basic technology of various digital signal p... [more] | RECONF2005-56 pp.19-24 |
| RECONF | 2005-11-30 16:35 |
Fukuoka | Kitakyushu International Conference Center | Adaptive Computling on the Dynamically Reconfigurable Processor DRP-1 Shohei Abe, Yohei Hasegawa (Keio Univ.), Takao Toi, Takeshi Inuo (NEC System Devices Research Labs.), Hideharu Amano (Keio Univ.) |
Adaptive computing is one of the power reduction methods to take full advantage of reconfigurable devices. The approach,... [more] | RECONF2005-57 pp.25-30 |
| RECONF | 2005-12-01 13:30 |
Fukuoka | Kitakyushu International Conference Center | Architecture Overview of Reconfigurable Processor FE-GA for Digital Media Processing Takanobu Tsunoda, Masashi Takada, Yohei Akita, Hiroshi Tanaka, Makoto Satoh, Masaki Ito (Hitachi) |
We developed a dynamically-reconfigurable processor Flexible Engine/Generic ALU array (FE-GA) targeting to digital media... [more] | RECONF2005-65 pp.37-41 |
| RECONF | 2005-12-01 14:45 |
Fukuoka | Kitakyushu International Conference Center | Mapping of FFT onto Reconfigurable Processor FE-GA Makoto Satoh, Hiroshi Tanaka, Takanobu Tsunoda, Masashi Takada, Yohei Akita, Masaki Ito (Hitachi, Ltd.) |
Dynamically reconfigurable processors are getting popular in the fields such as wireless LAN, Audio, and Video processin... [more] | RECONF2005-68 pp.55-60 |
| RECONF | 2005-12-02 09:30 |
Fukuoka | Kitakyushu International Conference Center | Development of a Reconfiguration Management Mechanism for Dynamically Reconfigurable System Takanori Susaki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
We have developed a dynamically reconfigurable system, which uses an embedded processor FPGA. In this system, an embedde... [more] | RECONF2005-72 pp.1-6 |
| RECONF | 2005-09-15 14:00 |
Hiroshima | Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor Yohei Hasegawa, Hideharu Amano, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan (Keio Univ.) |
Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that ... [more] | RECONF2005-35 pp.31-36 |
|
| RECONF | 2005-09-15 15:00 |
Hiroshima | Development of a partial reconfiguration controller for an embedded processor FPGA Isao Sakamoto, Takanori Susaki, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
We develop dynamically reconfigurable system，named EXPRESS-2，using partially reconfigurable FPGA. The FPGA contains one ... [more] | RECONF2005-37 pp.43-48 |
|
| RECONF | 2005-09-15 15:45 |
Hiroshima | Feasibility study on a run-time reconfigurable MPEG-2 decoder using functional separation Takeru Kisanuki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
Recently, the embeding apparatus represented by a cellular phone, PDA, etc. spreads very much, and its performance is al... [more] | RECONF2005-38 pp.49-54 |
|
| RECONF | 2005-05-13 15:45 |
Kyoto | Kyoto University | An Analysis of Fixed Point Arithmetic for DRP Miwa Miyata, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
Since Dynamically Reconfigurable Processor (DRP) has a lot of integer arithmetic units and small scale distributed memor... [more] | RECONF2005-25 pp.61-66 |
| RECONF | 2005-05-13 16:15 |
Kyoto | Kyoto University | Implementation of Active Direction-Pass Filter on Dynamically Reconfigurable Processor Shunsuke Kurotaki, Noriaki Suzuki (Keio Univ.), Kazuhiro Nakadai (HRI), Hiroshi G. Okuno (Kyoto Univ.), Hideharu Amano (Keio Univ.) |
A robot in real-world environments should have an ability to treat a mixture of multiple sound signals. Active Directi... [more] |
RECONF2005-26 pp.67-72 |
| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 10:10 |
Yamagata | An Image Recognition Processor Using Dynamically Reconfigurable ALU Naoto Miyamoto, Koji Kotani (Tohoku University), Kazuyuki Maruo (Advantest), Tadahiro Ohmi (Tohoku University) |
An image recognition processor implementing phase only correlation (POC) algorithm is proposed. Arithmetic logical unit ... [more] | SIP2004-91 ICD2004-123 IE2004-67 pp.13-18 |
|
[Return to Top Page]