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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2017-03-10
14:50		 Okinawa Kumejima Island Double-precision floating-point logarithm calculation method for FPGA
Yasufumi Fujiwara, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) CPSY2016-156 DC2016-102		 Floating-point arithmetic standard IEEE 754 was revised in 2008, and it presents 36 functions that should be calculated ... [more] CPSY2016-156 DC2016-102
pp.363-367
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
16:15		 Oita B-ConPlaza An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders
Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75		 In recent years, high speed and high precision computing is increasingly needed.
Hardware support for IEEE754 compliant... [more]		 CPSY2014-75
pp.19-23
DC, CPSY 2011-04-12
13:25		 Tokyo   A Note on Data Compression of Double-Precision Floating-Point Numbers for Massively Parallel Numerical Simulations
Mamoru Ohara, Takashi Yamaguchi (TIRI) CPSY2011-2 DC2011-2		 In numerical simulations using massively parallel computers like GPGPU (General-Purpose computing on Graphics Processing... [more] CPSY2011-2 DC2011-2
pp.5-10
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