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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2017-03-02
15:00		 Okinawa Okinawa Seinen Kaikan Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis
Xiaoguang Li, Mineo Kaneko (JAIST) VLD2016-118		 The performance of data path circuit can be improved by shifting the clock signal arrival time intentionally. In order t... [more] VLD2016-118
pp.85-90
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-28
15:35		 Oita B-ConPlaza Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56		 An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] VLD2014-102 DC2014-56
pp.203-208
RCS, AP, WBS, MW, MoNA 2005-03-02
15:50		 Kanagawa Yokosuka Research Park A study on frequency domain scheduling considering Quality of Service for OFDM Adaptive Modulation Systems
Sylvestre Demonget, Seiichi Sampei (Osaka Univ.) 		This paper proposes a frequency domain scheduling technique for the downlink of OFDM adaptive modulation-based broadband... [more] WBS2004-72 AP2004-253 RCS2004-340 MoMuC2004-123 MW2004-250
pp.95-100
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