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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2016-05-11
14:30		 Fukuoka Kitakyushu International Conference Center A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4		 In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] VLD2016-4
pp.41-46
VLD 2016-03-01
15:10		 Okinawa Okinawa Seinen Kaikan FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis
Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127		 Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] VLD2015-127
pp.93-98
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-28
16:00		 Oita B-ConPlaza A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures
Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57		 In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] VLD2014-103 DC2014-57
pp.209-214
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-29
17:00		 Kanagawa   Fast Module Placement in Floorplan-aware High-level Synthesis
Wataru Sato, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-107 CPSY2008-69 RECONF2008-71		 As device feature size decreases, interconnect delay becomes the dominating factor of total delay. Therefore it is neces... [more] VLD2008-107 CPSY2008-69 RECONF2008-71
pp.93-98
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-19
10:25		 Fukuoka Kitakyushu Science and Research Park A Multiplexer Reducing Algorithm in Floorplan-Aware High-level Synthesis for Distributed-Register Architectures
Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2008-84 DC2008-52		 In high level synthesis for resource shared architecture, multiplexers are inserted between registers and functional uni... [more] VLD2008-84 DC2008-52
pp.145-150
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-17
09:15		 Kanagawa Hiyoshi Campus, Keio University A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures
Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-119 CPSY2007-62 RECONF2007-65		 As device feature size decreases, interconnection delay becomes the dominating factor of total delay.
In addition, as ... [more]		 VLD2007-119 CPSY2007-62 RECONF2007-65
pp.7-12
 Results 1 - 6 of 6  /   
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