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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:30 |
Miyazaki | NewWelCity Miyazaki | On the design for testability method using Time to Digital Converter for detecting delay faults Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)  VLD2011-84 DC2011-60 |
We propose the design for testability method for detecting delay fault that can form a TDC(Time-to-Digital Converter) to... [more] | VLD2011-84 DC2011-60 pp.185-190 |
| DC | 2011-06-24 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
International Conference Report - VTS2011(29th IEEE VLSI Test Symposium) Kazumi Hatayama (NAIST) DC2011-11 |
This talk provide a report of VTS2011 (29th IEEE VLSI Test Symposium), which was held in Dana Point, California, USA, in... [more] | DC2011-11 pp.17-22 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2011-03-18 11:20 |
Okinawa | Design Method of Easily Testable Parallel Adders under Delay Constraints Shinichi Fujii (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-75 DC2010-74 |
Recently, with the development of VLSI design and manufacturing technology, the scale of integrated circuits on a VLSI c... [more] | CPSY2010-75 DC2010-74 pp.57-62 |
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| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 11:35 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology Hiroki Yosho, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2010-105 CPSY2010-60 RECONF2010-74 |
In general, an ATPG(Automatic Test Pattern Generation) is used to test LSI. However, because logic function and wiring r... [more] | VLD2010-105 CPSY2010-60 RECONF2010-74 pp.145-150 |
| ICD, ITE-IST | 2010-07-22 14:00 |
Osaka | Josho Gakuen Osaka Center | [Invited Talk]
Digitally-Assisted Analog Test Technology
-- Analog Circuit Test Technology in Nano-CMOS Era -- Haruo Kobayashi, Takahiro J. Yamaguchi (Gunma Univ.) ICD2010-27 |
This paper reviews current production testing issues for analog and mixed-signal SoC, and discusses the following: (i)... [more] |
ICD2010-27 pp.37-42 |
| DC | 2010-06-25 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] | DC2010-8 pp.1-6 |
| DC | 2010-06-25 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Class of Partial Thru Testable Sequential Circuits with Multiplexers Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-9 |
Partially thru testable sequential circuits are known to be practically testable, and a condition for the testable seque... [more] | DC2010-9 pp.7-11 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-28 14:35 |
Tokyo | A consideration of synthesis methods for easily testable parallel prefix adders Shinichi Fujii, Naofumi Takagi (Nagoya Univ.) CPSY2009-93 DC2009-90 |
Previously, synthesis methods of parallel prefix adders have been proposed. These methods primarily use circuit area and... [more] | CPSY2009-93 DC2009-90 pp.489-493 |
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| DC | 2010-02-15 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A binding method for testability based on resources sequential depth reduction Takaaki Cho, Toshinori Hosokawa (Nihon Univ.) DC2009-70 |
Behavioral descriptions are recently used for circuit designs on application specific fields. Behavioral synthesis is us... [more] | DC2009-70 pp.31-38 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 13:45 |
Kochi | Kochi City Culture-Plaza | A Yield Model with Testability and Repairability Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2009-54 DC2009-41 |
For deep-submicron technology, the increase in transitive and permanent faults of LSIs is a critical problem due to the ... [more] | VLD2009-54 DC2009-41 pp.89-94 |
| DC | 2009-06-19 10:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design method of easily testable parallel prefix adders Hidetoshi Suzuki, Naofumi Takagi (Nagoya Univ) DC2009-10 |
We propose a design method of easily testable parallel prefix adders. In a parallel prefix adder, the prefix computation... [more] | DC2009-10 pp.1-6 |
| DC | 2009-02-16 16:10 |
Tokyo | A Secure Scan Design Approach using Extended de Bruijn Graph Hideo Fujiwara, Marie Engelene J. Obien (NAIST) DC2008-78 |
Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. T... [more] | DC2008-78 pp.61-66 |
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| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:55 |
Fukuoka | Kitakyushu International Conference Center | An optimization of thru trees for test generation based on acyclical testability Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2007-72 DC2007-27 |
The class of acyclic sequential circuits is $\tau^2$-bounded, i.e., acyclic sequential circuits are practically easily t... [more] | VLD2007-72 DC2007-27 pp.13-18 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 14:15 |
Fukuoka | Kitakyushu International Conference Center | A design method for easily testable multipliers adaptable to various structures of partial product addition Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) VLD2007-83 DC2007-38 |
We propose a design method for easily testable multipliers. We construct partial product adders of a multiplier with t... [more] |
VLD2007-83 DC2007-38 pp.7-12 |
| ICD, IPSJ-ARC | 2007-06-01 11:00 |
Kanagawa | Design Techniques of Wave Pipelines Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) ICD2007-28 |
In order to improve rather complicated design and testing methods of wave-pipelines, our policy is to cover rough tuning... [more] | ICD2007-28 pp.67-72 |
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| ICD, IPSJ-ARC | 2006-06-08 15:30 |
Kanagawa | Design for Testability of Software-Based Self-Test for Processors Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) |
In this paper, we propose a design for testability method for test programs of software-based self-test using test progr... [more] | ICD2006-48 pp.49-54 |
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