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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2023-02-28 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
Test Point Selection Method Using Graph Neural Networks and Deep Reinforcement Learning Shaoqi Wei, Kohei Shiotani, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)  DC2022-87 |
It is well known that selecting the optimal test point to maximize the fault coverage is NP-hard. Conventional heuristic... [more] | DC2022-87 pp.27-32 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:20 |
Kumamoto | (Primary: On-site, Secondary: Online) |
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 |
In this study, we have proposed a method to make the design-for-testability circuity function as a security mechanism by... [more] | VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 pp.156-161 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 |
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] | VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 pp.162-167 |
| DC | 2021-02-05 15:30 |
Online | Online | A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2020-77 |
A field testing that monitors the values of circuit outputs and internal signal lines during function mode is used as on... [more] | DC2020-77 pp.48-53 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 17:30 |
Online | Online | An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-15 DC2020-15 |
In recent year, controller augmentation has been used for design-for-testability and design-for-security at register tra... [more] | CPSY2020-15 DC2020-15 pp.93-98 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 15:20 |
Ehime | Ehime Prefecture Gender Equality Center | A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.) VLD2019-43 DC2019-67 |
One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability... [more] | VLD2019-43 DC2019-67 pp.133-138 |
| DC, SS | 2019-10-24 16:00 |
Kumamoto | Kumamoto Univ. | A Non-scan Online Test Based on Covering n-Time State Transition Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) SS2019-19 DC2019-47 |
As one of the means to avoid the fault due to the deteriorate over time of VLSI, online test is used to monitor the outp... [more] | SS2019-19 DC2019-47 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42 |
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC. However, faulty TSVs ... [more] |
VLD2018-56 DC2018-42 pp.119-124 |
| DC | 2018-02-20 10:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79 |
TSV attracts attention as a new implementation method of interconnects between dies in 3DICs. However, faulty TSVs may ... [more] |
DC2017-79 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] | VLD2017-37 DC2017-43 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56 |
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures. ... [more] |
VLD2016-62 DC2016-56 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Easily-testable Carry Select Adder with Online Error Detection Capability Nobutaka Kito (Chukyo Univ.) VLD2015-72 DC2015-68 |
An easily testable multi-block carry select adder with online error detection capability is proposed. An easily testable... [more] | VLD2015-72 DC2015-68 pp.225-230 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | Investigation of the area reduction of observation part and control part in TSV fault detection circuit Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26 |
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] | VLD2014-72 DC2014-26 pp.3-8 |
| VLD | 2014-03-03 16:25 |
Okinawa | Okinawa Seinen Kaikan | Secure scan design using improved random order scans and its evaluations Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-141 |
Scan test using scan chains is one of the most important DFT techniques. On the other hand, scan-based attacks are repo... [more] |
VLD2013-141 pp.43-48 |
| DC | 2014-02-10 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Module Coupling Overhead Aware Scan Chain Construction Meguru Komatsu, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-79 |
It is necessary to minimize the impact on the layout of the design changes to Design for Testability (DFT). Especially,... [more] |
DC2013-79 pp.1-5 |
| DC | 2014-02-10 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2013-80 |
In recent deep sub-micron (DSM) ICs, it is difficult to detect open and short defects since they do not behave like co... [more] |
DC2013-80 pp.7-12 |
| DC | 2014-02-10 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] | DC2013-81 pp.13-18 |
| DC | 2013-02-13 13:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | On Fault detection method considering adjacent TSVs for a delay fault in TSV Masanori Nakamura, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ.of Tokushima) DC2012-85 |
We propose a fault detection method for a TSV (through-Silicon via) considering adjacent TSVs for detecting delay caused... [more] | DC2012-85 pp.31-36 |
| DC | 2012-02-13 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) DC2011-83 |
Quasi-Delay-Insensitive(QDI) design has been attracting attention as one of the practical techniques for implementation ... [more] | DC2011-83 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:00 |
Miyazaki | NewWelCity Miyazaki | Modeling Economics of LSI Design and Manufacturing for Selecting Test Design. Noboru Shimizu, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-71 DC2011-47 |
Many test designs (or DFTs: designs-for-testability) have been proposed to overcome some issues around LSI testing. In... [more] |
VLD2011-71 DC2011-47 pp.115-120 |
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