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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SS | 2017-03-09 09:30 |
Okinawa | A Symbolic Simulation of Dense-Timed Pushdown Automata with Clock Freezing Sho Hiraoka, Shoji Yuen (Nagoya Univ.)  SS2016-60 |
We present a symbolic simulation based on a zone construction for the dense timed pushdown automata with clock freezing(... [more] | SS2016-60 pp.1-6 |
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| IA, SITE, IPSJ-IOT [detail] | 2017-03-03 13:50 |
Okinawa | Culture Resort Festone (Okinawa) | Verification of Precise of Clock Synchronization using IEEE 1588 in Network Composed of Ordinary Routers Koki Horita (Keio Univ.), Shota Shiobara, Takao Okamawari (Softbank), Fumio Teraoka, Kunitake Kaneko (Keio Univ.) SITE2016-62 IA2016-92 |
In these days, demands for highly precise clock synchronization have been increasing. IEEE1588 (PTP), which aims for sub... [more] | SITE2016-62 IA2016-92 pp.13-18 |
| VLD | 2017-03-02 15:00 |
Okinawa | Okinawa Seinen Kaikan | Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis Xiaoguang Li, Mineo Kaneko (JAIST) VLD2016-118 |
The performance of data path circuit can be improved by shifting the clock signal arrival time intentionally. In order t... [more] | VLD2016-118 pp.85-90 |
| VLD | 2017-03-02 15:25 |
Okinawa | Okinawa Seinen Kaikan | Optimum Temperature Dependent Timing Skew for Temperature Aware Design Makoto Soga, Mineo Kaneko (JAIST) VLD2016-119 |
Electric devices equipping LSIs are widely distributed everywhere on the earth and the space, and LSIs are demanded to o... [more] | VLD2016-119 pp.91-96 |
| VLD | 2017-03-02 15:50 |
Okinawa | Okinawa Seinen Kaikan | MILP Approach to Skew-Aware High Level Synthesis Kai Shimura, Mineo Kaneko (JAIST) VLD2016-120 |
Intentional clock skew is known as one of the promising techniques for enhancing the circuit speed. However, when we tr... [more] |
VLD2016-120 pp.97-102 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 15:00 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) | A fully on-chip, ultra-low power RC oscillator with current mode architecture for real time clock applications Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) EMD2016-85 MR2016-57 SCE2016-63 EID2016-64 ED2016-128 CPM2016-129 SDM2016-128 ICD2016-116 OME2016-97 |
A compact and low-power current-mode RC oscillator (RCO) with process, voltage, and temperature (PVT) stability has been... [more] | EMD2016-85 MR2016-57 SCE2016-63 EID2016-64 ED2016-128 CPM2016-129 SDM2016-128 ICD2016-116 OME2016-97 pp.81-86 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 11:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | A Golden-IC Free Clock Tree Driven Authentication Approach for Hardware Trojan Detection Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST), Alex Orailoglu (UCSD) VLD2016-67 DC2016-61 |
Due to outsourcing of numerous stages of the IC manufacturing process in different foundries, security risks such as har... [more] | VLD2016-67 DC2016-61 pp.135-140 |
| MSS, CAS, IPSJ-AL [detail] | 2016-11-25 12:55 |
Hyogo | Kobe Institute of Computing | Formal Description of Synchronization by Functional Definition of Synchronous Circuits Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) CAS2016-73 MSS2016-53 |
Synchronous circuits are usually defined as D-Flipflop (D-FF) synchronized circuits, but it is doubtful that D-FF comple... [more] | CAS2016-73 MSS2016-53 pp.99-104 |
| CCS | 2016-11-04 15:55 |
Kyoto | Kyoto Sangyo Univ. (Musubiwaza Bldg.) | A mathematical model of the phase response change associated with desynchronization in the cell population of plant circadian system Kosaku Masuda, Ryuta Kitaoka, Kazuya Ukai, Hirokazu Fukuda (Osaka Pref. Univ.) CCS2016-38 |
Circadian clock is a non-linear oscillator system in nature. Circadian clock autonomously oscillates in constant conditi... [more] | CCS2016-38 pp.41-44 |
| DC, SS | 2016-10-27 15:05 |
Shiga | Hikone Kinro-Fukushi Kaikan Bldg. | Towards a Zone-based Verification for DTPDA with Clock Freezing Sho Hiraoka, Shoji Yuen (Nagoya Univ.) SS2016-25 DC2016-27 |
We present a zone construction for the dense timed pushdown automata with freezing ages as a discretization method to ve... [more] | SS2016-25 DC2016-27 pp.43-48 |
| SCE | 2016-08-08 14:15 |
Saitama | Saitama Univ. (Omiya sonic city) | Performance evaluation of TES microcalorimeter for Nuclear Clock Keisei Maehisa, Tasuku Hayashi, Haruka Muramatsu, Kazuhisa Mitsuda, Noriko Yamasaki (JAXA), Atsushi Yamaguchi (RIKEN), Kyousuke Maehata (Kyushu Univ.) SCE2016-19 |
(To be available after the conference date) [more] | SCE2016-19 pp.37-39 |
| RCS, RCC, ASN, NS, SR (Joint) |
2016-07-21 10:50 |
Aichi | [Poster Presentation]
Evaluation of Adaptability in Reflective Delay Tomography Using Compressed Sensing Teruhito Naka, Shinsuke Hara (Osaka City Univ.), Takahiro Matsuda (Osaka Univ.), Kenichi Takizawa, Fumie Ono, Ryu Miura (NICT) RCC2016-24 NS2016-58 RCS2016-111 SR2016-41 ASN2016-32 |
Delay tomography is a method to estimate link delays by means of measuring end-to-end path delays in a network. Delay to... [more] | RCC2016-24 NS2016-58 RCS2016-111 SR2016-41 ASN2016-32 pp.63-67(RCC), pp.45-49(NS), pp.93-97(RCS), pp.63-67(SR), pp.45-49(ASN) |
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| VLD, CAS, MSS, SIP | 2016-06-17 15:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Clock Distribution Network with Multiple Source Buffers for Stacked Chips Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 |
In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] | CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 pp.167-172 |
| OFT | 2016-05-27 09:55 |
Okayama | Okayama International Center | Self-Clocking Synchronized Optical Demultiplexing Using Four-Wave Mxing in a Quantum-Dot SOA Liang Yang, Tomoya Yatsu, Motoharu Matsuura (Univ. of Electro-Commun.) OFT2016-8 |
We demonstrated the optical demultiplexing using self-clocking synchronization. The demultiplexing was based on four-wav... [more] | OFT2016-8 pp.29-32 |
| COMP | 2016-04-22 10:20 |
Nara | Checkpointing and Rollback Using Lamport Clocks for Hybrid P2P Systems Sen Moriya (Kindai Univ.) COMP2016-1 |
The author considers a rollback algorithm for hybrid P2P systems which consist of multiple peers and a single server. Th... [more] | COMP2016-1 pp.1-8 |
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| IE, IMQ, MVE, CQ (Joint) [detail] |
2016-03-07 11:25 |
Okinawa | A Measurement Path Selection Method in Adaptive Reflective Delay Tomography Using Compressed Sensing Dai Komuro, Shinsuke Hara (Osaka City Univ.), Takahiro Matsuda (Osaka Univ.), Kenichi Takizawa, Fumie Ono, Ryu Miura (NICT) CQ2015-117 |
Delay tomography is a method to estimate internal node or link states by means of measuring end-to-end route delays in a... [more] | CQ2015-117 pp.55-60 |
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| DC | 2016-02-17 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech) DC2015-87 |
Both logic paths and clock paths are subject to the impact of IR-Drop which occurs in capture mode during scan test. Thi... [more] | DC2015-87 pp.7-12 |
| AI | 2015-12-04 14:35 |
Fukuoka | Kyutech-Salite | A Clock Map for Public Concern Visualization Method
-- Initial Proposal for Concern Visualization -- Takanari Matsuda, Masaharu Tsubokura, Yukio Ohsawa (Univ. of Tokyo) AI2015-20 |
This paper proposes a method for visualizing medical record with considering patients concerns. Our target focus is espe... [more] | AI2015-20 pp.47-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo) CPM2015-130 ICD2015-55 |
A quick-lock all-digital Clock-Data Recovery circuit that does not require a reference clock is propposed. Internal Tim... [more] |
CPM2015-130 ICD2015-55 pp.17-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
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