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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY | 2015-04-17 13:00 |
Tokyo | CGRA in Cache for Graph Applications Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)  CPSY2015-7 DC2015-7 |
Recently, CGRA has been suggested high-speed and lower power consumption of graph processing. Generally, CGRA is connect... [more] | CPSY2015-7 DC2015-7 pp.37-41 |
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| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
An Implementation of Web Cache System using Access Frequency of Content Pieces Takayuki Shiroma, Takuma Nakajima, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) ICD2014-80 CPSY2014-92 |
Developing efficient network platforms has been an important research task to deal with large volumes of contents growin... [more] | ICD2014-80 CPSY2014-92 pp.35-40 |
| CS | 2014-11-07 09:00 |
Hokkaido | Shiretoko (Hokkaido) | Time to Hold (TTH), an Optimal Cache Replacement Policy for Video Delivery on CCN Haipeng Li, Hidenori Nakazato (Waseda Univ.) CS2014-65 |
In-network caching, one of the characteristics of Content Centric Networking (CCN), allows the contents to be cached alo... [more] | CS2014-65 pp.69-74 |
| CPSY, DC | 2014-04-25 15:15 |
Tokyo | A Hardware Cache Mechanism for Column-Oriented Databases Akihiko Hamada, Hiroki Matsutani (Keio Univ.) CPSY2014-5 DC2014-5 |
A column-oriented store is one of structured storages (NOSQLs), in which a variable number of columns can be stored for... [more] |
CPSY2014-5 DC2014-5 pp.21-26 |
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| CQ, MoNA, IPSJ-DPS, IPSJ-CN, IPSJ-EIP (Joint) [detail] |
2013-09-12 14:25 |
Ishikawa | Kanazawa Institute of Technology | Traffic-based Flow Cache Port Separate Mechanism for Network Processor Hayato Yamaki, Hiroaki Nishi (Keio Univ.) CQ2013-36 |
A mechanism called Flow cache, which classifies packets into flows and caches the results of header rewrite that is equa... [more] | CQ2013-36 pp.47-52 |
| NS, IN (Joint) |
2013-03-07 11:10 |
Okinawa | Okinawa Zanpamisaki Royal Hotel | High quality streaming using disjoint paths under hierarchical cache-servers environment Akihiro Fujimoto, Yusuke Hirota (Osaka Univ.), Hideki Tode (Osaka Pref. Univ.), Koso Murakami (Osaka Univ.) NS2012-206 |
Video streaming using hierarchical cache servers is effective to provide high quality services to many users. However, w... [more] | NS2012-206 pp.237-242 |
| NS, IN (Joint) |
2013-03-08 10:50 |
Okinawa | Okinawa Zanpamisaki Royal Hotel | A Design of Sensor Data Storage System for Mobile Participatory Sensing Junya Niwa, Kazuya Okada, Takeshi Okuda, Youki Kadobayashi, Suguru Yamaguchi (NAIST) NS2012-214 |
The development of wireless technologies and the rapid growth of mobile devices equipped with sensors have enabled the p... [more] | NS2012-214 pp.283-288 |
| NS, IN (Joint) |
2013-03-08 11:30 |
Okinawa | Okinawa Zanpamisaki Royal Hotel | An OpenFlow Implementation of Multicast Distribution System Using In-network Cache Ryo Kawasumi, Yusuke Hirota (Osaka Univ.), Hideki Tode (Osaka Prefecture Univ.), Koso Murakami (Osaka Univ.) NS2012-248 |
With improvement of network performance, content distribution services such as live streaming has been spread. For thes... [more] |
NS2012-248 pp.483-488 |
| VLD | 2013-03-05 15:35 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.) VLD2012-151 |
This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of... [more] |
VLD2012-151 p.89 |
| NS, IN (Joint) |
2012-03-08 10:30 |
Miyazaki | Miyazaki Seagia | Energy Awareness based on Cache Allocation Management in Content-Centric Networking Satoshi Imai (Fujitsu lab.), Kenji Leibnitz (NICT), Masayuki Murata (Handai) IN2011-140 |
Power consumption of network devices has been increasing together with traffic volume and it is therefore important to f... [more] | IN2011-140 pp.19-24 |
| NS, IN (Joint) |
2012-03-09 11:00 |
Miyazaki | Miyazaki Seagia | Design of Time-Out Aging Cache for Bursty Traffic Souta Hatakeyama, Masaki Aida (TMU), Mika Ishizuka (NTT) IN2011-164 |
Ethernet is widely used in various situations. In this paper, we study a design method of time-out aging cache for appli... [more] | IN2011-164 pp.163-168 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:05 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.) SIP2011-76 ICD2011-79 IE2011-75 |
The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given ... [more] | SIP2011-76 ICD2011-79 IE2011-75 pp.89-94 |
| VLD | 2011-03-02 14:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118 |
In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO du... [more] |
VLD2010-118 pp.13-18 |
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
Design of Memory Access Controller for FU Array Accelerator Shunsuke Shitaoka, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-114 |
Our previously proposed FU (functional unit) array accelerator can achieve both high energy-efficiency and binary-compat... [more] | ICD2010-114 pp.95-96 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 09:30 |
Fukuoka | Kyushu University | Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-64 DC2010-31 |
The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded sys... [more] | VLD2010-64 DC2010-31 pp.55-60 |
| RCS, AN, MoNA, SR (Joint) |
2010-03-05 14:00 |
Kanagawa | YRP | Overlay and Clean Slate Technologies for Opportunistic Wireless Environments Ryoichi Shinkuma (Kyoto Univ.) RCS2009-318 MoMuC2009-91 SR2009-115 AN2009-84 |
Wireless access has been diversified; experienced transmission speed in wireless access dynamically changes depending on... [more] | RCS2009-318 MoMuC2009-91 SR2009-115 AN2009-84 pp.351-356(RCS), pp.101-106(MoMuC), pp.161-166(SR), pp.89-94(AN) |
| SIP, CAS, CS | 2010-03-02 13:45 |
Okinawa | Hotel Breeze Bay Marina, Miyakojima | [Poster Presentation]
Automatic Code Parallelization base on quantitative evaluation of data transfer for multi-layered cache architecture Takuya Noritake, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-119 SIP2009-164 CS2009-114 |
An automatic code parallelization method based on quantitative evaluation of data transfer for multi-layered cache archi... [more] | CAS2009-119 SIP2009-164 CS2009-114 pp.235-236 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 15:40 |
Kochi | Kochi City Culture-Plaza | Two-level Cache Simulation with L2 Unified Cache for Embedded Applications Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-47 DC2009-34 |
In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simula... [more] | VLD2009-47 DC2009-34 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 16:00 |
Kochi | Kochi City Culture-Plaza | Simulation-Based Bus Width Optimization for Two-Level Cache Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-48 DC2009-35 |
In this paper, we propose a simulation-based bus width and cache configuration optimization approach for two-level cache... [more] | VLD2009-48 DC2009-35 pp.43-48 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-05 15:45 |
Niigata | Sado Island Integrated Development Center | Single-Cycle-Accessible Two-Level Cache Architecture Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-91 DC2008-82 |
A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the ener... [more] | CPSY2008-91 DC2008-82 pp.19-24 |
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