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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HIP | 2023-10-11 10:25 |
Kyoto | Kyoto Keizai Center (Primary: On-site, Secondary: Online) |
The effects of a third person perspective on body image in VR environment Ninomiya Shun, Sato Mie, Kanari Kei (Utsunomiya Univ.)  HIP2023-69 |
We have a limited view of our own body from a first-person perspective, and this often leads to biases in body image. Th... [more] | HIP2023-69 pp.43-46 |
| MSS, CAS, SIP, VLD | 2020-06-18 14:00 |
Online | Online | Optimal Design for Level-Shifter-Less Approach using Channel Length Modulation & Body Biasing Tatsuya Watanabe, Usami Kimiyoshi (SIT) CAS2020-8 VLD2020-8 SIP2020-24 MSS2020-8 |
A multi-VDD design realizes LSIs to be low power by allowing to use multiple different power supply voltages. In this de... [more] | CAS2020-8 VLD2020-8 SIP2020-24 MSS2020-8 pp.41-46 |
| HWS, VLD | 2019-02-28 10:25 |
Okinawa | Okinawa Ken Seinen Kaikan | Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB Ryo Magasaki, Yusuke Yoshida (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2018-108 HWS2018-71 |
In recent years, IoT devices are rapidly increasing. One of the IoT devices is a sensor node and a small medical device... [more] | VLD2018-108 HWS2018-71 pp.91-96 |
| HWS, VLD | 2019-02-28 10:50 |
Okinawa | Okinawa Ken Seinen Kaikan | Single Supply Level Shifter Circuit using body-bias Yuki Takeyoshi, Kimiyoshi Usame (SIT) VLD2018-109 HWS2018-72 |
A multi-VDD scheme exists as a technique to realize low power consumption by using different power supply voltages. A ci... [more] | VLD2018-109 HWS2018-72 pp.97-102 |
| HWS, ISEC, SITE, ICSS, EMM, IPSJ-CSEC, IPSJ-SPT [detail] | 2018-07-26 14:10 |
Hokkaido | Sapporo Convention Center | Compensation of Temperature Induced Flipping-Bits in CMOS SRAM PUF by NMOS Body-Bias Xuanhao Zhang, Xiang Chen, Hanfeng Sun, Hirofumi Shinohara (Waseda Univ.) ISEC2018-41 SITE2018-33 HWS2018-38 ICSS2018-44 EMM2018-40 |
PUF suffers from flipping-bits caused by temperature changes which degrade the stability of output. This paper proposes ... [more] | ISEC2018-41 SITE2018-33 HWS2018-38 ICSS2018-44 EMM2018-40 pp.333-336 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami (SIT) VLD2017-33 DC2017-39 |
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In ... [more] | VLD2017-33 DC2017-39 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 13:10 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB) Shunsuke Kogure, Kimiyoshi Usami (Shibaura Institute of Tech) VLD2016-47 DC2016-41 |
Level shifter is a circuit that changes the voltage amplitude of the signal. It is essential to exchange signals with di... [more] | VLD2016-47 DC2016-41 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-53 DC2016-47 |
We focus on the Standard Cell Memory (SCM) as another option to supersede SRAM for low-voltage operation. This paper des... [more] | VLD2016-53 DC2016-47 pp.55-60 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 14:15 |
Osaka | Central Electric Club | Impacts of Flexible V_th control and Low Process Variability of SOTB to Ultra-low Voltage Designs Yasuhiro Ogasahara (AIST) SDM2016-65 ICD2016-33 |
This paper discusses impacts of flexible Vth control, low process variability, and steep SS with small on-current of new... [more] | SDM2016-65 ICD2016-33 pp.111-116 |
| VLD | 2016-03-01 16:40 |
Okinawa | Okinawa Seinen Kaikan | Optimization technique of substrate voltage for Dynamic Multi-Vth methodology in Silicon-on-thin BOX. Hanano Suzuki, Kimiyoshi Usami (Shibaura IT) VLD2015-129 |
Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] | VLD2015-129 pp.105-110 |
| VLD | 2016-03-01 17:05 |
Okinawa | Okinawa Seinen Kaikan | Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT) VLD2015-130 |
In recent years, energy harvesting and sensor node have attracted a lot of attention. Therefore, a memory which can redu... [more] | VLD2015-130 pp.111-116 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 09:25 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation and evaluation of Dynamic Multi-Vth methodology in Silicon-on-Thin-BOX Shohei Io, Hanano Suzuki, Shohei Nakamura, Kimiyoshi Usami (Shibaura IT) VLD2015-88 CPSY2015-120 RECONF2015-70 |
Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] | VLD2015-88 CPSY2015-120 RECONF2015-70 pp.91-96 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 10:55 |
Kanagawa | Hiyoshi Campus, Keio University | Power Reduction of TLB using Body Bias Control on SOTB Daiki Kawase, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2015-102 CPSY2015-134 RECONF2015-84 |
SOTB(Silicon on thin buried oxide) MOSFET is one of the FD-SOI device with 10nm BOX layer. SOTB effectively reduces the... [more] |
VLD2015-102 CPSY2015-134 RECONF2015-84 pp.191-196 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit Tomoaki Koide, Kouichirou Ishibashi (UEC), Nobuyuki Sugi (LEAP) CPM2015-134 ICD2015-59 |
The leakage has been increasing by miniaturization of the transistor in recently year. Adaptive body bias generator with... [more] | CPM2015-134 ICD2015-59 pp.39-43 |
| RECONF | 2015-06-20 14:00 |
Kyoto | Kyoto University | On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors Hanpei Koike, Masakazu Hioki, Yasuhiro Ogasahara (AIST), Hayato Ishigaki, Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST) RECONF2015-22 |
Flex Power FPGA utilizes threshold voltage programmability to reduce its static power by the body bias control of circui... [more] | RECONF2015-22 pp.119-124 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 08:30 |
Kagoshima | Power optimization of low-power reconfigurable accelerator CMA-SOTB Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano (Keio Univ.) CPSY2014-174 DC2014-100 |
(To be available after the conference date) [more] | CPSY2014-174 DC2014-100 pp.71-76 |
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| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 17:00 |
Kanagawa | Hiyoshi Campus, Keio University | Temperature sensor applying Body Bias in Silicon-on-Thin-BOX Tsubasa Kosaka, Shohei Nakamura, Kimiyoshi Usami (S.I.T.) VLD2014-127 CPSY2014-136 RECONF2014-60 |
The performance advancement by the transistor scaling is blocked by increase of power consumption and process variation.... [more] | VLD2014-127 CPSY2014-136 RECONF2014-60 pp.99-104 |
| SDM | 2014-11-07 11:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Quasi-Ballistic Transport Parameters in Si Double-Gate MOSFETs Extracted Using Monte Carlo Method Hideaki Tsuchiya, Ryoma Ishida (Kobe Univ.), Yoshinari Kamakura, Nobuya Mori (Osaka Univ.), Shigeyasu Uno (Ritsumeikan Univ.), Matsuto Ogawa (Kobe Univ.) SDM2014-105 |
Recently, we have developed a Monte Carlo simulator for accurately extracting quasi-ballistic transport parameters in MO... [more] | SDM2014-105 pp.53-58 |
| RECONF | 2014-06-12 11:40 |
Miyagi | Katahira Sakura Hall | Body bias control of low-power reconfigurable accelerator CMA-SOTB Yu Fujita, Hongliang Su, Hideharu Amano (Keio univ.) RECONF2014-8 |
For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator cal... [more] | RECONF2014-8 pp.37-42 |
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