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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY | 2015-04-17 13:25 |
Tokyo | A study of processor architecture suited for intelligent sensing system Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST)  CPSY2015-8 DC2015-8 |
Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] | CPSY2015-8 DC2015-8 pp.43-48 |
|
| DC | 2014-06-20 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Hierarchical Testability Using Results of Test Environment Generation Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-16 |
Hierarchical test generation methods using functional register-transfer level circuits have been proposed as efficient t... [more] | DC2014-16 pp.39-44 |
| RECONF | 2013-05-20 17:40 |
Kochi | Kochi Prefectural Culture Hall | Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Imagawa (Kyoto Univ.), Shinichi Noda, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2013-8 |
This paper proposes a mixed-grained reconfigurable architecture that supports C-based behavioral synthesis and flexibl... [more] |
RECONF2013-8 pp.41-46 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 10:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu) VLD2012-77 DC2012-43 |
In this paper, we propose behavioral synthesis methods for asynchronous pipelined circuits with bundled-data implementat... [more] | VLD2012-77 DC2012-43 pp.105-110 |
| RECONF | 2012-05-29 16:45 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) RECONF2012-14 |
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FP... [more] |
RECONF2012-14 pp.77-82 |
| VLD | 2012-03-06 14:00 |
Oita | B-con Plaza | A loop pipeling method for irregular nested loops Takashi Takenaka, Kazutoshi Wakabayashi (NEC), Yuka Nakagoshi (NIS) VLD2011-126 |
This paper presents a behavioral synthesis method for pipelining irregular nested loops. An irregular nested loop is ... [more] |
VLD2011-126 pp.37-42 |
| VLD | 2012-03-06 15:05 |
Oita | B-con Plaza | High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2011-128 |
It is widely known that high-level synthesis technology can improve the design productivity dramatically by raising the ... [more] | VLD2011-128 pp.49-54 |
| CAS | 2012-01-19 11:15 |
Fukuoka | Kyushu Univ. | [Invited Talk]
Design Methodology of Group Signature Circuits for Cloud Servers and Clients Sumio Morioka, Jun Furukawa, Yuichi Nakamura, Kazue Sako (NEC) CAS2011-90 |
Group signature is one of the main theme in recent digital signature studies. The scheme allows users to sign anonymousl... [more] | CAS2011-90 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 13:15 |
Fukuoka | Kyushu University | A case study of the effective value range analysis for Behavioral synthesis Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2010-32 |
The digital circuit becomes more complex and larger scale recently, and behavioral synthesis that use behavioral descri... [more] |
CPSY2010-32 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 11:25 |
Fukuoka | Kyushu University | A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) VLD2010-76 DC2010-43 |
Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very ha... [more] | VLD2010-76 DC2010-43 pp.143-148 |
| VLD | 2010-03-12 15:00 |
Okinawa | An ASIC implementation of a group signature algorithm using two-level behavioral synthesis Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako (NEC) VLD2009-128 |
We implemented a group signature algorithm, which enables anonymous digital signature, into an ASIC. To the best of the... [more] | VLD2009-128 pp.175-180 |
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| DC | 2010-02-15 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A binding method for testability based on resources sequential depth reduction Takaaki Cho, Toshinori Hosokawa (Nihon Univ.) DC2009-70 |
Behavioral descriptions are recently used for circuit designs on application specific fields. Behavioral synthesis is us... [more] | DC2009-70 pp.31-38 |
| VLD | 2009-03-11 14:25 |
Okinawa | Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) VLD2008-131 |
In this paper, a pipeline scheduling algorithm for minimizing total circuit area under throughput constraint is present... [more] |
VLD2008-131 pp.29-34 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-19 10:00 |
Fukuoka | Kitakyushu Science and Research Park | Variable Scheduling and Binding for High-Level Synthesis Considering Indefinite Cycle Operations Yuki Toda, Nagisa Ishiura, Kousuke Sone (Kwansei Gakuin Univ.) VLD2008-83 DC2008-51 |
This article presents variable scheduling and binding for high-level synthesis. Conventional scheduling algorithms deci... [more] |
VLD2008-83 DC2008-51 pp.139-144 |
| ISEC, SITE, IPSJ-CSEC | 2008-07-25 09:55 |
Fukuoka | Fukuoka Institute of System LSI Design Industry | Architecture Optimization of a Group Signature Circuit Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako, Isamu Teranishi (NEC) |
Group signature scheme is one of the most active research area in recent cryptographic algorithms/applications. Typical... [more] | ISEC2008-40 pp.37-44 |
| VLD, IPSJ-SLDM | 2008-05-08 15:50 |
Hyogo | Kobe Univ. | Improvement Technique of Binding for Multiplexer Reduction Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) |
In Behavioral Synthesis for resource shared architecture, multiplexers are inserted before registers andfunctional units... [more] | VLD2008-4 pp.19-24 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-27 11:15 |
Kagoshima | Partitioning Behavioral Descriptions Exploiting Function-Level Parallelism Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii (Nagoya Univ.) DC2007-90 CPSY2007-86 |
This paper proposes a method to efficiently generate hardware from a large behavioral description by behavioral synthesi... [more] | DC2007-90 CPSY2007-86 pp.37-42 |
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| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 14:15 |
Fukuoka | Kitakyushu International Conference Center | An Efficient Behavioral Synthesis Method Considering Specialized Functional Units Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.) VLD2007-98 DC2007-53 |
This paper proposes a novel Behavioral Synthesis method that improves a performance of synthesized circuits utilizing sp... [more] | VLD2007-98 DC2007-53 pp.55-60 |
| CAS, NLP | 2007-10-18 14:50 |
Tokyo | Musashi Institute of Technology | Derivation of Circuit Level Specifications of ΔΣ Modulator Based on Behavioral Modeling and Simulation Yasuji Ikeda, Hideki Asai (Shizuoka Univ.) CAS2007-47 NLP2007-75 |
A technique is presented for high-level synthesis using behavioral modeling of delta-sigma modulator. Verilog-A is used ... [more] | CAS2007-47 NLP2007-75 pp.73-77 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 11:25 |
Fukuoka | Kitakyushu International Conference Center | A Consideration of Chaining methods on Behavioral Synthesis Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.) |
In Behavioral Synthesis, operation chaining is one of the e±cient techniques to reduce the number of control steps. Alm... [more] |
VLD2005-65 ICD2005-160 DC2005-42 pp.25-30 |
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