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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 10:55 |
Aomori | Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII)  VLD2013-47 ICD2013-71 IE2013-47 |
There are mainly two types of handshaking protocols in asynchronous circuit design; 2-phase handshaking protocol and 4-p... [more] | VLD2013-47 ICD2013-71 IE2013-47 pp.7-12 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 10:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu) VLD2012-77 DC2012-43 |
In this paper, we propose behavioral synthesis methods for asynchronous pipelined circuits with bundled-data implementat... [more] | VLD2012-77 DC2012-43 pp.105-110 |
| IPSJ-SLDM, VLD | 2012-05-31 10:55 |
Fukuoka | Kitakyushu International Conference Center | Development of an FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation Keitaro Takizawa, Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) VLD2012-9 |
This paper proposes a design support tool set for asynchronous circuits with bundled-data implemen-tation which are impl... [more] | VLD2012-9 pp.49-54 |
| DC | 2012-02-13 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) DC2011-83 |
Quasi-Delay-Insensitive(QDI) design has been attracting attention as one of the practical techniques for implementation ... [more] | DC2011-83 pp.43-48 |
| RECONF | 2011-05-12 14:20 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation of Bundled-Data Asynchronous Circuits on FPGA and thier Performance Evaluation Tadashi Okabe (TIRI) RECONF2011-7 |
Asynchronous circuit design can solved many problems related to power consumption , EMI , clock skew and so on . Recentl... [more] | RECONF2011-7 pp.37-42 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | [Invited Talk]
Design of Asynchronous Circuits with Bundled-data Implementation on FPGA Hiroshi Saito (Univ. Aizu) VLD2010-107 CPSY2010-62 RECONF2010-76 |
This report initially introduces several researches related to asynchronous circuits and FPGAs. Then, this report propos... [more] | VLD2010-107 CPSY2010-62 RECONF2010-76 pp.157-162 |
| RECONF | 2010-09-17 10:15 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33 |
Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock t... [more] | RECONF2010-33 pp.91-95 |
| DC | 2010-06-25 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] | DC2010-8 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:40 |
Kochi | Kochi City Culture-Plaza | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | CPM2009-135 ICD2009-64 pp.7-12 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Tomohiro Yoneda (NII) DC2009-18 |
This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling und... [more] | DC2009-18 pp.1-6 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 14:45 |
Kanagawa | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-120 CPSY2008-82 RECONF2008-84 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | VLD2008-120 CPSY2008-82 RECONF2008-84 pp.171-176 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-19 11:15 |
Fukuoka | Kitakyushu Science and Research Park | Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors Koei Takada, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (U. of Tokyo) VLD2008-90 DC2008-58 |
Dual-rail four-phase asynchronous circuits are well-known for their benefits in terms of delay variation tolerance. On t... [more] | VLD2008-90 DC2008-58 pp.183-188 |
| NC | 2008-11-08 13:00 |
Saga | Saga Univ. | [Invited Talk]
Brain-inspired Integrated Systems with Time-domain Information Processing Takashi Morie, Hideki Tanaka, Daisuke Atuti, Keisuke Korekado, Kazuki Nakada (Kyushu Inst. of Tech.) NC2008-68 |
We have proposed merged analog-digital circuit architecture, which can perform multiply-and-accumulation and arbitrary n... [more] | NC2008-68 pp.55-60 |
| DC, CPSY | 2008-04-23 16:45 |
Tokyo | Tokyo Univ. | An approach to tolerating delay faults based on asynchronous circuits Tomohiro Yoneda (NII), Masashi Imai (Univ. of Tokyo), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Yuichi Nakamura (NEC) CPSY2008-10 DC2008-10 |
Recent advances in semiconductor process technologies cause new types of faults, which should be handled in order to obt... [more] | CPSY2008-10 DC2008-10 pp.55-60 |
| VLD, ICD | 2008-03-07 10:05 |
Okinawa | TiRuRu | A Self-timed Processor with Dynamic Voltage Scaling Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) VLD2007-158 ICD2007-181 |
As PVT variations get larger, synchronous circuits are getting less reliable and timing margins are getting larger. Self... [more] | VLD2007-158 ICD2007-181 pp.13-18 |
| ED, SDM | 2007-06-25 13:00 |
Overseas | Commodore Hotel Gyeongju Chosun, Gyeongju, Korea | [Invited Talk]
Requirements for Thin Film Transistor Circuits on Plastic Mitsutoshi Miyasaka, Hiroyuki Hara, Nobuo Karaki, Satoshi Inoue (Seiko Epson) |
The self-heating effect of thin film transistors (TFTs) is a serious problem when the TFT circuits are formed on a plast... [more] | |
| CPSY, DC | 2006-04-14 11:10 |
Tokyo | Takeda Hall | Hazard Checking of Asynchronous Circuits: A New Approach Frederic Beal (Tokyo Inst. of Tech.), Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah) |
We present a new framework to express the semantics of asynchronous circuits, and as an application, an algorithm that ... [more] |
CPSY2006-5 DC2006-5 pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-11-30 16:35 |
Fukuoka | Kitakyushu International Conference Center | A Discussion about Timing Signal Design Considering Delay Variation Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations become extremely large. There are many factors that cause delay varia... [more] |
VLD2005-59 ICD2005-154 DC2005-36 pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-11-30 17:00 |
Fukuoka | Kitakyushu International Conference Center | Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations will become more serious. Delay insensitive asynchronous dual-rail ci... [more] |
VLD2005-60 ICD2005-155 DC2005-37 pp.37-42 |
| SCE | 2004-10-22 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Advanced Design Approaches for SFQ Logic Circuits based on the Binary Decision Diagram Takanobu Nishigai, Maki Ito, Nobuyuki Yoshikawa (Yokohama National Univ.), Koji Obata, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) |
We have been developing a design methodology of SFQ logic circuits based on the binary decision diagram(BDD). In the pre... [more] | SCE2004-27 pp.13-18 |
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