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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2010-06-25 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST)  DC2010-8 |
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] | DC2010-8 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:40 |
Kochi | Kochi City Culture-Plaza | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | CPM2009-135 ICD2009-64 pp.7-12 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Tomohiro Yoneda (NII) DC2009-18 |
This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling und... [more] | DC2009-18 pp.1-6 |
|
| VLD | 2009-03-12 17:30 |
Okinawa | Asynchronous $\pm2^k$ Gray-Code Adder Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.) VLD2008-155 |
The topological property of Gray code, that only one bit of the code is changed when its representing integer is one inc... [more] | VLD2008-155 pp.171-176 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 14:45 |
Kanagawa | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-120 CPSY2008-82 RECONF2008-84 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | VLD2008-120 CPSY2008-82 RECONF2008-84 pp.171-176 |
|
| ICD | 2008-12-12 14:35 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | Asynchronous ±1 Gray-Code Adder Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.) ICD2008-124 |
The topological property of Gray Code, that only one bit of the code is changed when its representing integer is one inc... [more] | ICD2008-124 pp.113-118 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-19 11:15 |
Fukuoka | Kitakyushu Science and Research Park | Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors Koei Takada, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (U. of Tokyo) VLD2008-90 DC2008-58 |
Dual-rail four-phase asynchronous circuits are well-known for their benefits in terms of delay variation tolerance. On t... [more] | VLD2008-90 DC2008-58 pp.183-188 |
| NC | 2008-11-08 13:00 |
Saga | Saga Univ. | [Invited Talk]
Brain-inspired Integrated Systems with Time-domain Information Processing Takashi Morie, Hideki Tanaka, Daisuke Atuti, Keisuke Korekado, Kazuki Nakada (Kyushu Inst. of Tech.) NC2008-68 |
We have proposed merged analog-digital circuit architecture, which can perform multiply-and-accumulation and arbitrary n... [more] | NC2008-68 pp.55-60 |
| DC, CPSY | 2008-04-23 16:45 |
Tokyo | Tokyo Univ. | An approach to tolerating delay faults based on asynchronous circuits Tomohiro Yoneda (NII), Masashi Imai (Univ. of Tokyo), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Yuichi Nakamura (NEC) CPSY2008-10 DC2008-10 |
Recent advances in semiconductor process technologies cause new types of faults, which should be handled in order to obt... [more] | CPSY2008-10 DC2008-10 pp.55-60 |
| VLD, ICD | 2008-03-07 10:05 |
Okinawa | TiRuRu | A Self-timed Processor with Dynamic Voltage Scaling Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) VLD2007-158 ICD2007-181 |
As PVT variations get larger, synchronous circuits are getting less reliable and timing margins are getting larger. Self... [more] | VLD2007-158 ICD2007-181 pp.13-18 |
| ED, SDM | 2007-06-25 13:00 |
Overseas | Commodore Hotel Gyeongju Chosun, Gyeongju, Korea | [Invited Talk]
Requirements for Thin Film Transistor Circuits on Plastic Mitsutoshi Miyasaka, Hiroyuki Hara, Nobuo Karaki, Satoshi Inoue (Seiko Epson) |
The self-heating effect of thin film transistors (TFTs) is a serious problem when the TFT circuits are formed on a plast... [more] | |
| CPSY, DC | 2006-04-14 11:10 |
Tokyo | Takeda Hall | Hazard Checking of Asynchronous Circuits: A New Approach Frederic Beal (Tokyo Inst. of Tech.), Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah) |
We present a new framework to express the semantics of asynchronous circuits, and as an application, an algorithm that ... [more] |
CPSY2006-5 DC2006-5 pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-11-30 16:35 |
Fukuoka | Kitakyushu International Conference Center | A Discussion about Timing Signal Design Considering Delay Variation Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations become extremely large. There are many factors that cause delay varia... [more] |
VLD2005-59 ICD2005-154 DC2005-36 pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-11-30 17:00 |
Fukuoka | Kitakyushu International Conference Center | Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations will become more serious. Delay insensitive asynchronous dual-rail ci... [more] |
VLD2005-60 ICD2005-155 DC2005-37 pp.37-42 |
| COMP | 2005-10-18 10:25 |
Miyagi | Tohoku Univ. | An asynchronous cellular space in which synchronous reversible cellular automata can be embedded Jin-Shan Qi, Kenichi Morita (Hiroshima Univ.) |
We proposed a 2-dimensional 2-state asynchronous cellular automaton in which asynchronous logic elements called a rotary... [more] | COMP2005-38 pp.15-20 |
| COMP | 2005-09-15 10:00 |
Osaka | Osaka Univ., Toyonaka Campus | A construction method of synchronous reversible cellular automata using simple asynchronous logic elements Jin-Shan Qi, Kenichi Morita (Hiroshima Univ.) |
We proposed a new method of realizing a synchronous reversible partitioned cellular automaton concisely, which is comput... [more] | COMP2005-29 pp.9-16 |
| SCE | 2004-10-22 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Advanced Design Approaches for SFQ Logic Circuits based on the Binary Decision Diagram Takanobu Nishigai, Maki Ito, Nobuyuki Yoshikawa (Yokohama National Univ.), Koji Obata, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) |
We have been developing a design methodology of SFQ logic circuits based on the binary decision diagram(BDD). In the pre... [more] | SCE2004-27 pp.13-18 |
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