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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CAS, MSS, IPSJ-AL [detail] | 2014-11-20 10:40 |
Okinawa | Nobumoto Ohama Memorial Hall (Ishigaki island) | An asynchronous serial multiplier for digital fearing aid Masafumi Kondo, Daichi Okamoto (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Tomoyuki Yokogawa, Kazutami Arimoto (Okayama Prefectural Univ.)  CAS2014-89 MSS2014-53 |
Recently, digital hearing aids with digital signal processor (DSP) become widely used because of increasing of hearing i... [more] | CAS2014-89 MSS2014-53 pp.11-16 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 14:15 |
Miyagi | Hierarchical GALS system based on ring segmented bus architecture Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-63 ICD2014-56 IE2014-42 |
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed as an asynchronous bus a... [more] | VLD2014-63 ICD2014-56 IE2014-42 pp.19-24 |
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| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 15:10 |
Hokkaido | Hokkaido University | A distributed asynchronous arbiter for ring segmented bus type GALS systems Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 |
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. Howeve... [more] | CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 pp.237-242 |
| RECONF | 2014-06-12 10:50 |
Miyagi | Katahira Sakura Hall | An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6 |
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] | RECONF2014-6 pp.27-30 |
| VLD, IPSJ-SLDM | 2014-05-29 11:05 |
Fukuoka | Kitakyushu International Conference Center | Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu) VLD2014-5 |
This paper proposes a synthesis flow for asynchronous circuits with bundled-data implementation from a SystemC model to ... [more] | VLD2014-5 pp.21-26 |
| CPSY, DC | 2014-04-25 13:00 |
Tokyo | [Fellow Memorial Lecture]
Synchronous Circuit Design vs. Asynchronous Circuit Design
-- Trials to compare them from various aspects -- Tomohiro Yoneda (NII) CPSY2014-1 DC2014-1 |
In this talk, the asynchronous design, where execution is controlled in an event driven manner based on handshaking with... [more] | CPSY2014-1 DC2014-1 p.1 |
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| CPSY, DC | 2014-04-25 14:00 |
Tokyo | Construction of Design Environment for Asynchronous Circuits using DDL Cell Library Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2 |
As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging eff... [more] | CPSY2014-2 DC2014-2 pp.3-8 |
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| VLD | 2014-03-05 14:55 |
Okinawa | Okinawa Seinen Kaikan | A Design Method of Mixed Synchronous-Asynchronous Circuit Kotaro Kato, Mineo Kaneko (JAIST) VLD2013-164 |
In this paper, we have studied a design method of a mixed synchronous asynchronous circuit. In the proposed method, the ... [more] | VLD2013-164 pp.165-170 |
| DC | 2014-02-10 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] | DC2013-81 pp.13-18 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 11:40 |
Kanagawa | Hiyoshi Campus, Keio University | Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.) VLD2013-109 CPSY2013-80 RECONF2013-63 |
As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been p... [more] | VLD2013-109 CPSY2013-80 RECONF2013-63 pp.43-48 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 10:55 |
Aomori | Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2013-47 ICD2013-71 IE2013-47 |
There are mainly two types of handshaking protocols in asynchronous circuit design; 2-phase handshaking protocol and 4-p... [more] | VLD2013-47 ICD2013-71 IE2013-47 pp.7-12 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 10:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu) VLD2012-77 DC2012-43 |
In this paper, we propose behavioral synthesis methods for asynchronous pipelined circuits with bundled-data implementat... [more] | VLD2012-77 DC2012-43 pp.105-110 |
| IPSJ-SLDM, VLD | 2012-05-31 10:55 |
Fukuoka | Kitakyushu International Conference Center | Development of an FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation Keitaro Takizawa, Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) VLD2012-9 |
This paper proposes a design support tool set for asynchronous circuits with bundled-data implemen-tation which are impl... [more] | VLD2012-9 pp.49-54 |
| DC | 2012-02-13 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) DC2011-83 |
Quasi-Delay-Insensitive(QDI) design has been attracting attention as one of the practical techniques for implementation ... [more] | DC2011-83 pp.43-48 |
| NLP | 2012-01-24 09:45 |
Fukushima | Aizu-keiko-do Hall | An Asynchronous Sequential Logic Inner Hair Cell Model and its Response Characteristics Hironori Ishimoto, Hiroyuki Torikai (Osaka Univ.) NLP2011-135 |
In the mammalian inner ear, the basilar membrane vibrates in response to a sound wave and the inner hair cells transform... [more] | NLP2011-135 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki | NewWelCity Miyazaki | Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application Takao Kawano (Tohoku Univ.), Naoya Onizawa (McGill Univ.), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.) VLD2011-89 DC2011-65 |
In this paper, a new fine-grained power-gating technique is proposed. Fine-grained power-gating technique has the potent... [more] | VLD2011-89 DC2011-65 pp.215-220 |
| RECONF | 2011-05-12 14:20 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation of Bundled-Data Asynchronous Circuits on FPGA and thier Performance Evaluation Tadashi Okabe (TIRI) RECONF2011-7 |
Asynchronous circuit design can solved many problems related to power consumption , EMI , clock skew and so on . Recentl... [more] | RECONF2011-7 pp.37-42 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | [Invited Talk]
Design of Asynchronous Circuits with Bundled-data Implementation on FPGA Hiroshi Saito (Univ. Aizu) VLD2010-107 CPSY2010-62 RECONF2010-76 |
This report initially introduces several researches related to asynchronous circuits and FPGAs. Then, this report propos... [more] | VLD2010-107 CPSY2010-62 RECONF2010-76 pp.157-162 |
| RECONF | 2010-09-17 10:15 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33 |
Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock t... [more] | RECONF2010-33 pp.91-95 |
| CPSY, DC (Joint) |
2010-08-03 - 2010-08-05 |
Ishikawa | Kanazawa Cultural Hall | Fault-Resilient Multiple-Valued Asynchronous Data-Transfer Scheme Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu (Tohoku Univ.) DC2010-15 |
In this paper, we propose an asynchronous data-transmission scheme which is robust against wire-fault on the communicati... [more] | DC2010-15 pp.7-11 |
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