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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:10 |
Online | Online | A Multilayer Perceptron Training Accelerator using Systolic Array Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara (Toyko Tech)  VLD2021-23 ICD2021-33 DC2021-29 RECONF2021-31 |
Neural networks are being used in various applications, and the demand for fast training with large amounts of data is e... [more] | VLD2021-23 ICD2021-33 DC2021-29 RECONF2021-31 pp.37-42 |
| EMT, IEE-EMT | 2021-11-05 13:00 |
Online | Online | A Study on Numerical Analysis of Resistive Wall Wake fields in Accelerator Beam Pipes using Boundary Element Method Kazuhiro Fujita (Saitama IT) EMT2021-44 |
A better understanding of electromagnetic interaction of relativistic electron beams with resistive walls of accelerator... [more] | EMT2021-44 pp.82-87 |
| OPE, MW, IEE-EMT, MWP, EST, EMT, THz [detail] | 2021-07-16 15:20 |
Online | Online | A Study on Boundary Element Analysis of Accelerator Beam Pipes with Walls of Finite Conductivity Kazuhiro Fujita (SIT) EMT2021-27 MW2021-32 OPE2021-21 EST2021-28 MWP2021-29 |
Recent high-energy particle accelerators and X-ray free electron laser projects need a better understanding of electroma... [more] | EMT2021-27 MW2021-32 OPE2021-21 EST2021-28 MWP2021-29 pp.105-108 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| HWS, VLD [detail] | 2021-03-04 14:15 |
Online | Online | Experiments of Data Authenticity Verification in Multi-Node IoT Systems Using Elliptic Curve Digital Signature Chips Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) VLD2020-85 HWS2020-60 |
Practicality of IoT systems requires the efficiency and speed of crypto processing in edge nodes and remote servers. So ... [more] | VLD2020-85 HWS2020-60 pp.97-101 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 15:15 |
Online | Online | A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) VLD2020-49 CPSY2020-32 RECONF2020-68 |
In recent years, CNN has been used for various tasks in the field of computer vision and has achievedexcellent performan... [more] | VLD2020-49 CPSY2020-32 RECONF2020-68 pp.58-62 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 09:25 |
Online | Online | FPGA Accelerator Design for Real-Time Object Detection Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba) VLD2020-56 CPSY2020-39 RECONF2020-75 |
This paper presents a FPGA accelerator design for a real-time object detection algorithm using MASSD (Multi-Scale Attent... [more] | VLD2020-56 CPSY2020-39 RECONF2020-75 pp.96-100 |
| NS, IN (Joint) |
2020-03-06 15:10 |
Okinawa | Royal Hotel Okinawa Zanpa-Misaki (Cancelled but technical report was issued) |
Experimental results of soft error effect on a network equipment with error collection and detection function Mizuki Tateno, Kousuke Watanabe (NTT) NS2019-251 |
Due to the integration and miniaturization of semiconductor devices in compact and high performance communication devic... [more] | NS2019-251 pp.419-423 |
| SAT, SANE (Joint) |
2020-02-20 13:50 |
Okinawa | Performance evaluation of distributed parallel backprojection for stripmap SAR imaging on various accelerators Masato Gocho, Noboru Oishi (Mitsubishi Electric) SANE2019-114 |
This paper presents a performance evaluation of the distributed parallel backprojection for stripmap sar imaging on vari... [more] | SANE2019-114 pp.85-89 |
|
| SAT, SANE (Joint) |
2020-02-20 14:15 |
Okinawa | Acceleration Techniques for Chirp Z-Transform using AI-accelerator Ken Mitobe, Saki Matsuo, Masato Gocho, Akira Kakitani, Masashi Shiraishi (MELCO) SANE2019-115 |
When integrating a received signal of a frequency division MIMO (Multi input Multi output) radar, an integration loss oc... [more] | SANE2019-115 pp.91-95 |
|
| SDM | 2020-01-28 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Can in-memory/Analog Accelerators be a Silver Bullet for Energy-efficient Inference? Jun Deguchi, Daisuke Miyashita, Asuka Maki, Shinichi Sasaki, Kengo Nakata, Fumihiko Tachibana, Ryuichi Fujimoto (KIOXIA) SDM2019-85 |
This presentation introduces and discuss recent trends on in-memory/analog computing for deep learning inference, which ... [more] | SDM2019-85 p.11 |
| SDM, ICD, ITE-IST [detail] | 2019-08-07 13:30 |
Hokkaido | Hokkaido Univ., Graduate School /Faculty of Information Science and | [Invited Talk]
A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka (Hitachi) SDM2019-36 ICD2019-1 |
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The ... [more] | SDM2019-36 ICD2019-1 pp.1-5 |
| CPSY, DC, IPSJ-ARC [detail] | 2019-07-26 11:25 |
Hokkaido | Kitami Civic Hall | Inter-Node Direct Memory Access Performance with Distributed Switch for Full-Mesh Connection Between Accelerators with Optical Hub Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino (PETRA) CPSY2019-32 DC2019-32 |
In order to improve communication performance for paralle processing, we have proposed an optical hub that connects node... [more] | CPSY2019-32 DC2019-32 pp.171-176 |
| HWS, VLD | 2019-03-01 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
| RECONF | 2018-09-18 14:50 |
Fukuoka | LINE Fukuoka Cafe Space | Data Flow Representation and its Applications to Machine Learning Accelerator Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32 |
Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to r... [more] | RECONF2018-32 pp.73-78 |
| COMP | 2017-08-18 11:05 |
Aomori | Study of Evaluation Method of FPGA Accelerator for In-memory Columnar DB in Speed-up of Online Analytical Processing (OLAP) Tetsuro Hommura, Yoshifumi Fujikawa (Hitachi) COMP2017-14 |
Recently, real time analysis, which uses fresher data than ever before, is the trend. It is expected to be used in vario... [more] | COMP2017-14 pp.9-16 |
|
| COMP | 2017-08-18 11:40 |
Aomori | Study of the Method of Dictionary Encoding for Column Data in FPGA Accelerator for the In-Memory Columnar Database Yoshifumi Fujikawa, Tetsuro Hommura (Hitachi) COMP2017-15 |
Recently, real time analysis, which uses fresher data than ever before, is the trend. It is expected to be used in vari... [more] | COMP2017-15 pp.17-23 |
|
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 11:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Evaluation of the PEACH3 used for communication in application Takahiro Kaneda (Keio Univ.), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ.) VLD2016-83 CPSY2016-119 RECONF2016-64 |
Tightly Coupled Accelerators(TCA) architecture connects a number of GPUs directly through PCI Express using dedicated sw... [more] | VLD2016-83 CPSY2016-119 RECONF2016-64 pp.91-96 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2016-69 DC2016-63 |
We propose data transfer optimization in accelerator design with high-level synthesis. Typical accelerator designs perfo... [more] | VLD2016-69 DC2016-63 pp.147-152 |
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