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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, ICD [detail] 2021-10-19
10:00		 Online Online Evaluations of tamper resistance by Wave-FF for Power Analysis Attack on AES
Tomoaki Ukezono (Fukuoka Univ.) HWS2021-41 ICD2021-15		 Dual-Rail design represented by WDDL can be mentioned as a countermeasure against information leakage from power consump... [more] HWS2021-41 ICD2021-15
pp.1-6
RECONF 2012-09-18
13:20		 Shiga Epock Ritsumei 21, Ritsumeikan Univ. [Invited Talk] The LSI Design Methodology of Tamper Resistant Cryptographic Circuit
Takeshi Fujino, Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Uiv.) RECONF2012-29		 Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant t... [more] RECONF2012-29
pp.31-36
DC, CPSY 2011-04-12
14:30		 Tokyo   [Invited Talk] Tamper LSI Design Methodology Resistant to Malicious Attack
Takeshi Fujino, Mitsuru Shiozaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.) CPSY2011-4 DC2011-4		 Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant t... [more] CPSY2011-4 DC2011-4
pp.17-22
VLD 2011-03-03
10:20		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique
Katsuhiko Iwai, Kenji Kojima, Mitsuru Shiozaki, Syunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.) VLD2010-126		 Some secure DPA-resistant techniques to protect from Side-Channel Attack such as Differential Power Analysis (DPA) have ... [more] VLD2010-126
pp.57-62
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