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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:05 |
Kagoshima | Improved via programmable structured ASIC VPEX3S
-- Improvement of basic logic element to improve operation speed -- Taku Otani, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)  VLD2013-70 DC2013-36 |
We have been studying via programmable structured ASIC architecture “VPEX3(Via Programmable Logic using Exclusive-OR Arr... [more] | VLD2013-70 DC2013-36 pp.75-80 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:55 |
Kagoshima | Evaluation of Via Programmable Device named VPEX using benchmark circuits Shota Ueguchi, Ryohei Hori, Taku Otani (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-72 DC2013-38 |
Non-Recurring engineering cost including photo-mask cost increases with LSI process minimization. We have been studied v... [more] | VLD2013-72 DC2013-38 pp.87-92 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 09:40 |
Kagoshima | The design of Via Programmable Analog(VPA) circuit and its performance evaluation compared to programmable analog circuit Keisuke Ueda, Ryohei Hori, Mitsuru Shiozaki, Toshio Kumamoto, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ.) CPM2013-110 ICD2013-87 |
Recently, programmable analog circuits are started to be used because initial development cost including mask cost is re... [more] | CPM2013-110 ICD2013-87 pp.13-18 |
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| VLD | 2011-03-04 15:55 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-147 |
We have developed a via programmable logic device using exclusive-or array (VPEX). In a VPEX, the logic is changed using... [more] | VLD2010-147 pp.183-188 |
| VLD | 2010-03-11 10:00 |
Okinawa | Study of Via Programmable Logic Device VPEX for wiring architecture and Logic Array Block Shouta Yamada, Yuuichi Kokushou, Tomohiro Nishimoto, Naoyuki Yoshida, Ryohei Hori, Naoki Matsumoto, Tatsuya Kitamori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2009-107 |
We have developed the via-programmable logic device VPEX which was optimized for EB direct writing, and also developed t... [more] | VLD2009-107 pp.49-54 |
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| VLD | 2010-03-11 10:25 |
Okinawa | Examination of the best basic logic gate architecture for Via programmable logic device Ryohei Hori, Yuuichi Kokushou, Tomohiro Nishimoto, Shouta Yamada, Naoyuki Yoshida, Naoki Matsumoto, Takeshi Fujino (Ritsumei Univ.), Masaya Yoshikawa (Meijo Univ.) VLD2009-108 |
The structured ASIC on which the logic can be customized with a few mask layers, have been studied in order to reduce in... [more] | VLD2009-108 pp.55-60 |
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| VLD | 2010-03-11 10:50 |
Okinawa | Wiring delay of Logic Element used in Via programmable logic device VPEX Tomohiro Nishimoto, Tatsuya Kitamori, Yuuichi Kokushou, Shouta Yamada (Ritsumeikan Univ), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ) VLD2009-109 |
We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic elem... [more] | VLD2009-109 pp.61-66 |
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| VLD | 2009-03-12 09:15 |
Okinawa | Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Shouta Yamada (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyou Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2008-139 |
We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic elem... [more] | VLD2008-139 pp.77-82 |
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| ICD | 2008-12-12 13:45 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | Improvement of Logic Element used in Via programmable logic device VPEX Tomohiro Nishimoto, Masahide Kawarasaki, Eiji Hasegawa, Tomohiro Terakawa, Takeshi Fujino (Ritsumei Univ) ICD2008-122 |
We have been studied the via-programmable device (Via Programmable logic using EXclusive or array) whose logic element c... [more] | ICD2008-122 pp.101-106 |
| ICD | 2008-12-12 14:10 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | The Development of CAD Design Tools for Via Programmable Logic Device VPEX Yuuichi Kokushou, Masahide Kawarasaki, Kouta Ishibashi, Tomohiro Nishimoto, Kazuma Kitamura (Ritsumeikan Univ), Masaya Yoshikawa (Meijyou Univ), Takeshi Fujino (Ritsumeikan Univ) ICD2008-123 |
We have been studied the user-programmable device called VPEX(Via Programmable logic using Exclusive or array) which can... [more] | ICD2008-123 pp.107-112 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:00 |
Fukuoka | Kitakyushu International Conference Center | Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-80 DC2007-35 |
We propose the user-programmable device called VPEX (Via Programmable logic device using EXclusive-or array) which can c... [more] | VLD2007-80 DC2007-35 pp.61-66 |
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