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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY | 2016-12-16 14:20 |
Tokyo | Tokyo Institute of Technology | [Invited Talk]
A Data-Driven Processor Realizing Trillion Sensors Universe Hiroaki Nishikawa (Univ. of Tsukuba)  ICD2016-96 CPSY2016-102 |
This paper introduces a data-driven processor aiming at realizing Trillion Sensors Universe. Execution control scheme in... [more] | ICD2016-96 CPSY2016-102 pp.139-144 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 16:05 |
Aomori | A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ) VLD2013-52 ICD2013-76 IE2013-52 |
This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a co... [more] | VLD2013-52 ICD2013-76 IE2013-52 pp.29-34 |
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| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition Yuki Miyamoto, Guangji He, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ) ICD2012-101 |
This paper describes a low-power VLSI chip for 60-kWord continuous speech recognition based on a context-dependent Hidde... [more] | ICD2012-101 pp.49-53 |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 09:25 |
Iwate | Hotel Ruiz | Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size Yoshichika Fujioka (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.) VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki | NewWelCity Miyazaki | A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Reconginion Takanobu Sugahara, Guangji He, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) CPM2011-164 ICD2011-96 |
We have developed a low power VLSI chip for 60k-word real-time continuous speech recognition based on HMM(Hidden Markov ... [more] | CPM2011-164 ICD2011-96 pp.79-84 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| SIS | 2010-12-02 15:15 |
Nara | Circuit Design of a 128-point FFT Processor Using Pipeline MDC Architecture for 8x8 MIMO-OFDM Receivers Atsushi Orikasa, Yoshikazu Miyanaga, Shingo Yoshizawa (Hokkaido Univ.) SIS2010-45 |
This report presents a VLSI architecture of 128-point FFT in a 8x8 MIMO-OFDM receiver. A pipeline FFT processor based on... [more] | SIS2010-45 pp.59-64 |
|
| PRMU | 2009-12-18 15:40 |
Tochigi | Fujihara Cultural Center | A Real-Time 3D Motion Field Generation System employing Directional-Edge Histogram Matching VLSI Processors Seungho Shin, Tadashi Shibata (Univ. of Tokyo.) PRMU2009-153 |
In this paper, we will present a new system that detects three-dimensional motion fields very efficiently based on the V... [more] | PRMU2009-153 pp.83-88 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Development of a Stream Cipher Engine Chip Takumi Ishihara, Harunobu Uchiumi, Yusuke Osumi, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) ICD2009-94 |
One of crucial points for next generation ubiquitous network is to keep the temporary security without relying on perman... [more] | ICD2009-94 pp.95-100 |
| ICD | 2009-12-15 10:00 |
Shizuoka | Shizuoka University (Hamamatsu) | [Invited Talk]
A New VLSI System Architecture Mimicking the Processing in the Mind Tadashi Shibata (Univ. of Tokyo.) ICD2009-95 |
The performance of a today’s computer is really marvelous. It can carry out a prodigious amount of numerical calculation... [more] | ICD2009-95 pp.101-109 |
| CPM | 2009-08-11 14:20 |
Aomori | Hirosaki Univ. | Development of a Stream Cipher Engine Takumi Ishihara, Harunobu Uchiumi, Yusuke Osumi, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) CPM2009-49 |
One of crucial points for ubiquitous network is to keep the temporary security without relying on permanent network infr... [more] | CPM2009-49 pp.83-88 |
| ICD, ITE-CE | 2007-12-14 10:20 |
Kochi | A VGA 30-fps Real-Time Optical-Flow Processor Core for Moving Picture Recognition Hajime Ishihara, Masayuki Miyama (Kanazawa Univ.), Yuichiro Murachi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.), Yoshio Matsuda (Kanazawa Univ.) ICD2007-131 |
This paper proposes an optical-flow processor for real-time video recognition. This processor is based on the Pyramidal ... [more] | ICD2007-131 pp.65-70 |
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| MSS, CAS | 2007-11-30 14:30 |
Niigata | Niigata University | Code System for Rectangular Packing in 2D Torus Space Takayuki Shibata, Mineo Kaneko (JAIST) CAS2007-80 CST2007-31 |
We encounter rectangular packing in 2D Torus space in VLSI layout where the same set of components is placed repeatedly ... [more] | CAS2007-80 CST2007-31 pp.37-42 |
| ICD, IPSJ-ARC | 2007-06-01 16:15 |
Kanagawa | Design of a highly parallel VLSI processor based on functional-unit-level packet data transfer scheme Yoshichika Fujioka, Nobuhiro Tomabechi (Hachinohe Inst. Tech.), Michitaka Kameyama (Tohoku Univ.) ICD2007-34 |
Until now, network on chip technology based on course grain packet data transfer was proposed. In this paper, fine grain... [more] | ICD2007-34 pp.103-108 |
|
| CAS | 2005-01-19 10:45 |
Ishikawa | Kanazawa Univ | A Polynomial Time Algorithm for Embedding Graphs into Ladder with Minimum Congestion Tomohiro Ikeda, Akira Matsubayashi (Kanazawa Univ.) |
The problem of efficiently implementing parallel algorithms into parallel computers can be formulated as the graph embed... [more] | CAS2004-61 pp.7-12 |
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