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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY | 2011-10-21 09:50 |
Hyogo | Study of Mixed Power Gating on VLIW Processors Yoshifumi Ishii, Weihan Wang, Hideharu Amano (Keio Univ.)  CPSY2011-26 |
Power Gating (PG) is an effective way to reduce leakage power that becomes a big issue in LSI designs. There are two way... [more] | CPSY2011-26 pp.7-12 |
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| VLD | 2011-03-02 13:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | An Architecture Exploration Method based on a Branch-and-Bound Strategy for Embedded VLIW Processors Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-116 |
This paper proposes an architecture exploration method based on a branch-and-bound strategy for embedded VLIW processors... [more] | VLD2010-116 pp.1-6 |
| VLD | 2011-03-02 13:35 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-117 |
Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is... [more] | VLD2010-117 pp.7-12 |
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
Design of An FU Network for Array Accelerators Suguru Ooue, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-115 |
We have proposed Linear Array Pipeline Processor (LAPP) as a special implementation of Function Unit (FU) array based ac... [more] | ICD2010-115 pp.97-99 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 09:50 |
Fukuoka | Kyushu University | Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-65 DC2010-32 |
Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is... [more] | VLD2010-65 DC2010-32 pp.61-66 |
| VLD | 2009-03-11 10:30 |
Okinawa | Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2008-126 |
This article presents an optimum code scheduling method for digital signal processor SPXK5 taking account of its archite... [more] | VLD2008-126 pp.1-6 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 12:45 |
Kanagawa | A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-116 CPSY2008-78 RECONF2008-80 |
In this paper, we propose an energy-efficient ASIP synthesis method based on reducing instruction memory access. Since a... [more] | VLD2008-116 CPSY2008-78 RECONF2008-80 pp.147-152 |
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| CPSY | 2008-12-18 13:15 |
Kyoto | KYOTO Research Park | [Special Invited Talk]
An Introduction of Our Recent Research on VLIW from 3way to 9Nway Yasuhiko Nakashima (NAIST) CPSY2008-48 |
The first VLIW revealed as a hardware structure that could directly execute horizontal micro codes has been raised to on... [more] | CPSY2008-48 pp.31-36 |
| ICD, IPSJ-ARC | 2008-05-14 09:00 |
Tokyo | A Scalable Multi-core Processor for Mobile Multimedia Applications Hiroyuki Usui, Shuou Nomura, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Jun Tanabe, Masato Uchiyama, Takashi Miyamori, Yoshiro Tsuboi (Toshiba) ICD2008-25 |
We implemented multi-core processor for mobile multimedia applications. Each core consists of 32bit RISC processor and t... [more] | ICD2008-25 pp.39-44 |
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| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 16:50 |
Kanagawa | Hiyoshi Campus, Keio University | VLIW Extension of Software Development Environment Construction Tool ArchC Takanori Morimoto (Kwansei Gakuin Univ.), Takahiro Kumura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) VLD2007-134 CPSY2007-77 RECONF2007-80 |
ArchC is a C++/SystemC-based open-source software，which generates software development environments (consisting of Binut... [more] | VLD2007-134 CPSY2007-77 RECONF2007-80 pp.95-100 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 14:55 |
Fukuoka | Kitakyushu International Conference Center | Cycle Partitioned Scheduling for Code Optimization of VLIW DSP Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2007-102 DC2007-57 |
This paper proposes a cycle partitioned scheduling method for code optimization of VLIW DSPs. The previously proposed op... [more] | VLD2007-102 DC2007-57 pp.79-84 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 15:20 |
Fukuoka | Kitakyushu International Conference Center | Retargetable Linear Assembler for VLIW Processor Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.) VLD2007-103 DC2007-58 |
This paper proposes a retargetable linear assembler as a software development tool for custom VLIW processors. The ret... [more] |
VLD2007-103 DC2007-58 pp.85-90 |
| CPSY | 2005-12-16 15:15 |
Tochigi | Academia Hall, Utsunomiya Univ. | An Extendable Simulation Environment for Chip-Multi VLIW Architecture Design Fumihito Furukawa (Teikyo Univ.), Takayuki Aoki, Daisuke Oka, Atsushi Tsukikawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
Chip-multi VLIW architecture is promising in both of execution performance and power consumption. To explore such archit... [more] | CPSY2005-39 pp.37-42 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 11:20 |
Miyagi | Ichinobo, Sakunami-Spa | [Invited Talk]
Development of Image Recognition Processor Based on Configurable Processor Takashi Miyamori (Toshiba) |
We developed an image recognition processor, “Visconti,” based on a configurable processor. Three VLIW processors that e... [more] | SIP2005-121 ICD2005-140 IE2005-85 pp.37-42 |
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