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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2014-12-19 15:10 |
Toyama | Studies on Reliability Evaluation Techniques for Triple Register Circuits Naoki Midorikawa, Muneyuki Nakamura, Aromhack Saysanasongkham, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)  DC2014-72 |
This paper discusses the reliability evaluation technique for the triple register circuit which our research group had p... [more] | DC2014-72 pp.29-32 |
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| DC | 2014-06-20 15:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Fault Tolerant Response Analyzer for Built-in Self-test Yuki Fukazawa (Mie Univ.), Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2014-14 |
Reliable built-in self-test (Reliable BIST) is a scheme in which embedded BIST circuits are designed to be tolerant of t... [more] | DC2014-14 pp.27-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 15:20 |
Kagoshima | A controller design in high-level synthesis for multi-cycle transient fault tolerance Yutaro Ishimori, Tatsuya Nakaso, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2013-68 DC2013-34 |
This work discusses a design of the controller in a multi-cycle transient fault tolerant system. It focuses especially ... [more] |
VLD2013-68 DC2013-34 pp.45-50 |
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| DC, CPSY (Joint) |
2013-08-01 18:00 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Evaluation of Transient-Error-Tolerant Dependable Processors based on Multiplexed Registers Naoki Midorikawa, Yoshifumi Koyama (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metropolitan Univ.) DC2013-20 |
Recently, highly reliable design technique for processors which have transient error tolerance are presented for various... [more] | DC2013-20 pp.21-25 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis Tatsuya Nakaso, Ryoko Ohkubo, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-84 DC2012-50 |
Due to the increase in the integration, operational speed and application complexity, the tolerance for transient faul... [more] |
VLD2012-84 DC2012-50 pp.147-152 |
| CPSY, DC | 2012-04-10 13:00 |
Tokyo | A Processor to Tolerate Periodical Transient Faults under Highly Electromagnetic Environment by Using Built in Self Test Masahiko Negishi, Aromhack Saysanasongkham, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) CPSY2012-1 DC2012-1 |
This paper releases a report of the application for the fault tolerant sequential circuit technique against the periodic... [more] | CPSY2012-1 DC2012-1 pp.1-6 |
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| DC | 2011-10-20 11:30 |
Tokyo | A Study on Sequential Circuits Tolerating for Transient Faults in a Highly Electromagnetic Environment Aromhack Saysanasongkham, Kenta Imai, Yoshifumi Koyama, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) DC2011-21 |
Recently, research on miniaturizing and densifying the power converter circuit are showing significant progressions. Con... [more] | DC2011-21 pp.7-11 |
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| DC, CPSY | 2011-04-12 13:00 |
Tokyo | An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults Satoshi Fukumoto, Kenta Imai, Hideo Kohinata, Masayuki Arai (Tokyo Metropolitan Univ.) CPSY2011-1 DC2011-1 |
This paper discusses the extension of highly reliable technique for sequential circuits using duplicate register which h... [more] | CPSY2011-1 DC2011-1 pp.1-4 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 14:50 |
Fukuoka | Kyushu University | A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2010-60 DC2010-27 |
As the advance in semiconductor technology, the issue of soft errors, which are transient glitches caused by particle st... [more] | VLD2010-60 DC2010-27 pp.25-30 |
| DC, CPSY | 2010-04-13 16:20 |
Tokyo | Improvement of Transient-Fault-Tolerant Scheme for Out-of-Order Superscalar Processors Satoshi Arima, Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima, Shuichi Sakai (The Univ. of Tokyo) CPSY2010-5 DC2010-5 |
The feature size of LSI is getting smaller year by year, increasing random variation between the elements. To overcome t... [more] | CPSY2010-5 DC2010-5 pp.21-26 |
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| DC, CPSY | 2009-04-21 11:00 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults Hideo Kohinata, Kohei Marumoto, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) CPSY2009-1 DC2009-1 |
This paper proposes a novel technique to improve the reliability of sequential circuits. The proposed technique adopts t... [more] | CPSY2009-1 DC2009-1 pp.1-6 |
| DC | 2008-06-20 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Design of Highly Dependable Processor with the Tolerance to Multiple Simultaneous Transient Faults Makoto Kimura, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metroplitan Univ.) DC2008-13 |
We propose the methodology to make a highly reliable processor against multiple simultaneous transient faults. In our pr... [more] | DC2008-13 pp.13-18 |
| EE | 2006-07-13 15:40 |
Tokyo | Failure Analysis and Simulation of Electrical Power System for Satellite Go Segami, Hiroaki Kusawake, Yasuhiro Shimizu, Koichi Kibe (JAXA) EE2006-15 |
Fault tolerant desigen is necessary for satellite because we can’t repair anything in space if there is something wrong ... [more] | EE2006-15 pp.35-39 |
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| CPSY | 2004-12-20 16:05 |
Tokyo | Ochanomizu University | Towards Zero-Performance-Loss Microarchitecture for Transient Faults Tolerance Toshinori Sato (Kyushu Inst. Tech.) |
This paper presents an approach for integrating fault-tolerance techniques into microprocessors. Smaller and smaller tra... [more] | CPSY2004-60 pp.73-78 |
| NLP, CAS | 2004-09-13 15:15 |
Kyoto | Kyoto Univ. | Transient dynamics due to discontinuous solutions in electric power system with dc transmission Yoshihiko Susuki, Takashi Hikihara (Kyoto Univ.), Hsiao-Dong Chiang (Cornell Univ.) |
This report addresses transient dynamics and stability of an electric power system with dc transmission. When the trans... [more] | CAS2004-25 NLP2004-37 pp.21-26 |
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