| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2016-06-20 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.)  DC2016-14 |
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] | DC2016-14 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 13:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) VLD2015-40 DC2015-36 |
The Neighborhood Pattern Sensitive Fault (NPSF) is widely discussed fault model for memories, and it occurs when a memor... [more] | VLD2015-40 DC2015-36 pp.19-24 |
| CCS | 2015-08-07 10:45 |
Hokkaido | Dai-ichi Takimotokan (Noboribetsu, Hokkaido) | Discrete Fourier Transform Test Based on the Simultaneous Use of Multiple Sequences Hiroki Okada, Ken Umeno (Kyoto Univ.) CCS2015-42 |
In this paper, we review the problems in the Discrete Fourier Transform (DFT) test included in SP800-22 released by ... [more] |
CCS2015-42 pp.73-78 |
| MI | 2015-07-14 13:30 |
Hokkaido | Sun Refle Hakodate | Automatic Artery Extraction in Ultrasound Images for the aid of FMD test Kaori Nomura (NIT), Hiroshi Masuda (UNEX), Kazumasa Sano (Toe), Toshihiko Koyama (DENSO), Hidenori Suzuki (UNEX), Hidekata Hontani (NIT) MI2015-32 |
The authors propose a method for automatically extracting and tracking an artery region in a ultrasound temporal image ... [more] |
MI2015-32 pp.1-6 |
| DC | 2014-06-20 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Hierarchical Testability Using Results of Test Environment Generation Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-16 |
Hierarchical test generation methods using functional register-transfer level circuits have been proposed as efficient t... [more] | DC2014-16 pp.39-44 |
| DC | 2014-06-20 16:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An evaluation for Testability of Functional k-Time Expansion Models Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17 |
A test generation method using functional k-time expansion models for data paths was proposed. In the test generation m... [more] |
DC2014-17 pp.45-50 |
| DC | 2014-02-10 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Suitable Power-Aware Test Pattern Ordering for Deterministic Circular Self Test Path Ryo Ogawa, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-82 |
The power consumption of Very Large Scale Integrated circuit (VLSI) testing is a significant problem. The VLSI should be... [more] | DC2013-82 pp.19-24 |
| QIT (2nd) |
2013-11-19 16:10 |
Tokyo | Waseda Univ. | Quantum Hypothesis Testing and an Operational Interpretation of the Quantum Renyi Relative Entropies Milan Mosonyi (BME), Tomohiro Ogawa (UEC) |
In quantum information theory, we can consider various analogues of the classical Renyi relative entropy, among which th... [more] | |
| DC | 2013-06-21 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10 |
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] | DC2013-10 pp.1-6 |
| IT | 2013-05-24 14:45 |
Fukui | Hotel Matuya Sensen at Awara-onsen, Fukui Pref. | String complexity based on reduplicative parsing and its application to randomness testing Shigeru Maya, Hirosuke Yamamoto (Univ. of Tokyo) IT2013-8 |
A randomness test based on LZ-compelxity was included in the NIST statistical test suite. However, it was removed becaus... [more] | IT2013-8 pp.35-40 |
| NLP | 2012-11-19 14:20 |
Miyagi | Ishinomaki Senshu University | Study on Testing for Randomness of Pseudo-Random Number Sequence with NIST SP800-22 rev.1a Hitoaki Yoshida, Takeshi Murakami (Iwate Univ.), Satoshi Kawamura (Ishinomaki Senshu Univ.) NLP2012-78 |
NIST Special Publication 800-22, Statistical Test Suite for Random and Pseudo-random Number Generators for Cryptographic... [more] | NLP2012-78 pp.13-18 |
| NC, MBE (Joint) |
2011-03-08 14:35 |
Tokyo | Tamagawa University | Improved Granger causality tests for network structure estimation from time-series data Hikaru Harima, Shigeyuki Oba, Shin Ishii (Kyoto Univ.) NC2010-178 |
Granger causality and its variants have been proposed for estimating network structure as a causality graph based on cor... [more] | NC2010-178 pp.301-306 |
| DC | 2011-02-14 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-65 |
Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral sy... [more] | DC2010-65 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 16:25 |
Fukuoka | Kyushu University | Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2010-63 DC2010-30 |
Built-in Self Test (BIST) is one of effective methods for testing today's very large-scale SoCs.In BIST scheme, a t... [more] | VLD2010-63 DC2010-30 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 11:25 |
Fukuoka | Kyushu University | A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) VLD2010-76 DC2010-43 |
Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very ha... [more] | VLD2010-76 DC2010-43 pp.143-148 |
| DC | 2010-02-15 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Pattern Re-Ordering for Thermal-Uniformity during Test Makoto Nakao, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-66 |
Power consumption during VLSI testing varies spatially and temporally, and it leads to temperature variation during tes... [more] | DC2009-66 pp.7-12 |
| DC | 2009-12-11 13:25 |
Shimane | Note on Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test Anis Uzzaman (Cadence Design Systems/Tokyo Metro. Univ), Brion Keller, Tom Snethen (Cadence), Kazuhiko Iwasaki, Masayuki Arai (Tokyo Metro. Univ) DC2009-57 |
This paper describes how we provide a mean for dealing with the programmable aspects of on-product clock generation (OPC... [more] | DC2009-57 pp.7-12 |
|
| VLD, IPSJ-SLDM | 2009-05-20 15:20 |
Fukuoka | Kitakyushu International Conference Center | A scan test generation method to reduce the number of detected untestable faults Hiroshi Ogawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) VLD2009-3 |
There are faults which can be detected by only the invalid test patterns. This is one of the causes for the overtesting.... [more] | VLD2009-3 pp.13-18 |
| MI | 2008-09-17 14:10 |
Kyoto | Shimadzu Corp. | Determination of starting point for Logan graphical analysis using run test to improve PET neuroreceptor quantification Hiroto Ogaki (Chiba Univ), Yuichi Kimura, Mika Naganawa (NIRS), Muneyuki Sakata (TMIG), Miho Sidahara (NIRS), Mikio Suga (Chiba Univ) MI2008-40 |
This study aims at developing an algorithm to estimate a starting point, t*, for Logan Graphical Analysis (LGA). LGA is ... [more] | MI2008-40 pp.27-31 |
| ISEC | 2008-05-16 10:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A New Randomness Test Based on All the Autocorrelation Values Kenji Hamano, Hirosuke Yamamoto (Tokyo Univ.) ISEC2008-4 |
Discrete Fourier transform test (dft test) included in the NIST randomness test suite, and autocorrelation test included... [more] | ISEC2008-4 pp.23-30 |
[Return to Top Page]