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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 18 of 18  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2024-02-21
15:50
Tokyo Tokyo University-Hongo-Engineering Bldg.4
(Primary: On-site, Secondary: Online)
[Invited Talk] Recent Studies of WoW and CoW Cu-Cu Hybrid Bonding
Yoshihisa Kagawa, Yukako Ikegami, Takahiro Kamei, Hayato Iwamoto (SSS) SDM2023-87
In recent years, a variety of 3D stacked devices have been proposed. The Cu-Cu hybrid bonding that can realize high dens... [more] SDM2023-87
pp.31-35
AP 2021-03-26
11:35
Online Online [Invited Talk (Young Researcher)] Study of optically transparent antennas based on graphene
Shohei Kosuga (Aoyama Gakuin Univ./JSPS Research Fellow), Shunichiro Nagata, Sho Kuromatsu, Ryosuke Suga, Takeshi Watanabe, Osamu Hashimoto, Shinji Koh (Aoyama Gakuin Univ.) AP2020-137
We focused on graphene, a one-atom-thick two dimensional carbon sheet, as an electrode material for optically transparen... [more] AP2020-137
pp.31-36
SDM 2021-02-05
14:25
Online Online [Invited Talk] Impacts of Misalignment on 1um Pitch Cu-Cu Hybrid Bonding
Yoshihisa Kagawa, Takumi Kamibayashi, Masaki Haneda, Nobuotoshi Fujii, Syunsuke Furuse, Hideto Hashiguch, Tomoyuki Hirano, Hayato Iwamoto (SSS) SDM2020-58
In this study, we have successfully demonstrated the 1um pitch Cu-Cu hybrid bonding technology with remarkable electrica... [more] SDM2020-58
pp.15-18
SDM 2020-02-07
14:55
Tokyo Tokyo University-Hongo [Invited Talk] A THIN BONDING MATERIAL FOR HIGH DENSITY HETEROGENEOUS INTEGRATION
Yasuhisa Kayaba, Yuzo Nakamura, Jun Kamada, Takashi Kozeki, Kazuo Kohmura (MCI) SDM2019-95
A new thin bonding material was developed for the heterogeneous device chip integration by Cu-Cu hybrid bonding. The bon... [more] SDM2019-95
pp.31-34
NLP, CCS 2018-06-10
14:00
Kyoto Kyoto Terrsa Prediction of Foreign Exchange Rates by Price Quotations of Counterparty Banks -- Using Collective Intelligence of Professional Views --
Takehiro Suzuki, Tomoya Suzuki (Ibaraki Univ.) NLP2018-47 CCS2018-20
In foreign-exchange (FX) dealing, FX brokers basically cancel out the orders from their customers to prevent the price f... [more] NLP2018-47 CCS2018-20
pp.109-114
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:50
Kumamoto Kumamoto-Kenminkouryukan Parea Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking
Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2017-42
In recent years,Three-dimensional (3D) field-programmable gate arrays(FPGAs) are expected to offer higher logic density ... [more] RECONF2017-42
pp.31-36
MRIS, ITE-MMS 2016-12-09
10:30
Ehime Ehime Univ. Sputter-deposition of inclined anisotropy film with Co/Pt atomic layer stacking
Naoki Honda (Tohoku Inst. Tech.), Shintaro Hinata, Shin Saito (Tohoku Univ.) MR2016-38
Deposition of weakly inclined anisotropy film for bit-patterned media was studied. First, deposition of Co/Pt layer stac... [more] MR2016-38
pp.51-56
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-29
10:55
Osaka Ritsumeikan University, Osaka Ibaraki Campus Development of power estimation tool for three dimensional FPGA
Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] RECONF2016-46
pp.35-40
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
17:30
Kanagawa Hiyoshi Campus, Keio University A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) VLD2014-152 CPSY2014-161 RECONF2014-85
The inductive-coupling 3D chip stacking technique has several advantages over TSV-based 3D stacking. For example, its ma... [more] VLD2014-152 CPSY2014-161 RECONF2014-85
pp.245-250
MRIS, ITE-MMS 2014-12-12
09:50
Ehime Ehime Univ. Stacking structure dependence of magnetic properties of Co/Pt layer stacked film sputter - deposited at room temperature
Taruho Tsuchiya, Naoki Honda, Hironaga Uchida (Tohoku Inst Tech), Shin Saito, Shintaro Hinata (Tohoku Univ) MR2014-38
Preparation of L11 ordered Co-Pt film with atomic layer stacking was investigated using room temperature sputtering aimi... [more] MR2014-38
pp.59-64
SDM 2014-06-19
11:05
Aichi VBL, Nagoya Univ. Control of Stacking Fault Structures in Ge1-xSnx Epitaxial Growth
Takanori Asano (Nagoya Univ.), Noriyuki Taoka (IHP Microelectronics), Osamu Nakatsuka, Shigeaki Zaima (Nagoya Univ.) SDM2014-47
Ge or Ge1-xSnx layer with (110) surface has attracted much attentions for Ge multi-gate MOS transistors. For forming a h... [more] SDM2014-47
pp.21-25
VLD 2014-03-05
11:15
Okinawa Okinawa Seinen Kaikan Inductive-Coupling Interface for Multiple-Memory Chip Stacking
Mitsuko Saito, Tadahiro Kuroda (Keio Univ.) VLD2013-159
Inductive-coupling interface for multiple-memory chip stacking is proposed. The number of stacked memory chips was limit... [more] VLD2013-159
pp.137-140
MRIS, ITE-MMS 2013-12-12
16:15
Ehime Ehime Univ. Deposition of Co/Pt film with perpendicular magnetic anisotropy by layer stacking sputtering
Taruho Tsuchiya, Naoki Honda (Tohoku Inst. of Tech.) MR2013-30
Low temperature preparation of Co/Pt stacked film with high magnetic anisotropy was studied using atomic layer stacking ... [more] MR2013-30
pp.33-38
MRIS, ITE-MMS 2012-07-20
09:50
Ibaraki Ibaraki Univ. Perfect Hcp Atomic-layer Stacking for Sputtered Co Film with c-plane Sheet Texture by Substrate Heating Sputtering
Naoki Nozawa, Shin Saito, Shintaro Hinata, Migaku Takahashi (Tohoku Univ.) MR2012-16
Effects of substrate heating of Co sputtered film with c-plane sheet texture on atomic-layer stacking were investigated ... [more] MR2012-16
pp.41-46
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-30
10:25
Fukuoka Kyushu University [Invited Talk] System Performance Improvement Expected for 3D LSI Chip Stacking Integration Technology
Masahiro Aoyagi (AIST) CPM2010-134 ICD2010-93
3D LSI chip stacking integration technology using through-Si-via is very promising for future electronic hardware integr... [more] CPM2010-134 ICD2010-93
pp.61-65
ITE-MMS, MRIS 2010-07-08
14:30
Ibaraki Ibaraki Univ. [Invited Talk] Development of Pseudo-hcp Thin Films for Perpendicular Recording Media
Shin Saito, Migaku Takahashi (Tohoku Univ.) MR2010-15
Measurement of the stacking faults (SFs) formed in a pseudo-hexagonal closed packed (pseudo-hcp) film is proposed using ... [more] MR2010-15
pp.17-24
ICD 2010-04-23
15:40
Kanagawa Shonan Institute of Tech. A 2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NAND-Flash Memory Stacking
Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda (Keio Univ.) ICD2010-19
128 chips are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2Gb/s by ind... [more] ICD2010-19
pp.99-102
ITE-MMS, MRIS 2009-06-11
14:15
Miyagi RIEC Tohoku Univ. Uniaxial magnetocrystalline anisotropy of c-plane oriented Co100-xGex film with pseudo-hcp structure
Shintaro Hinata, Shin Saito, Ryuichi Yanagisawa, Migaku Takahashi (Tohoku Univ.) MR2009-2
Effects of Ge addition into Co sputtered film on uniaxial magnetocrystalline anisotropy energy (Ku) were investigated. T... [more] MR2009-2
pp.5-8
 Results 1 - 18 of 18  /   
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